Samsung S3C6400X User Manual page 1122

S3C6400X RISC MICROPROCESSOR
IRDA INTERUPT IDENTIFICATION REGISTER(IRDA_IIR)
Register Address
IrDA _IIR 0x7F00_7010
IrDA _IIR
Last byte to Rx FIFO
Error indication
Tx Underrun
Last byte detect
Rx overrun
Last byte read from Rx
FIFO
Tx FIFO below
threshold
Rx FIFO over threshold
R/W
R IrDA Interrupt Identification Register
Bit
[7] Last byte write to RX FIFO interrupt pending. When the
last payload byte of the frame is loaded into the RX FIFO,
bit 7 is set to '1'. Bit 7 is set prior to bit 2. Bit 7 is cleared
[6] Receiver line error Indication. Bit 6 is set to a '1' if one of
three possible errors occurs in the RX process. With the
corresponding interrupt enable bit active, one of PHY,
CRC and Frame length errors let this bit go active. Bit 6 is
cleared when the source of the error is cleared.
[5] Transmit under-run interrupt pending. When
corresponding interrupt enable bit is active, bit 5 is set to
'1' if an under-run occurs in TX FIFO. Bit 5 is cleared by
[4] Detects last byte of a frame interrupt pending. If the
corresponding interrupt enable bit is active, bit 4 is set to
'1' when the demodulation block detects the last byte of a
received frame and the CRC decoding is finished. Bit 4 is
[3] RX FIFO over-run interrupt. When corresponding interrupt
enable bit is set, bit3 is active, bit 3 is set to '1' when an
overrun occurs in the RX FIFO. Bit 3 is cleared by serving
[2] RX FIFO last byte read interrupt. When corresponding
interrupt enable bit is active, it is set to '1' when the CPU
reads the last byte of a frame from the RX FIFO. It is
[1] TX FIFO below threshold interrupt pending. Bit 1 is set to
'1' when the transmitter FIFO level is below its threshold
[0] RX FIFO over threshold interrupt pending. Bit 0 is set to '1'
when the receiver FIFO level is equal to or above its
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
when it is read.
serving the under-run.
cleared when it is read.
the over-run.
cleared when it is read.
level.
threshold level.
IRDA
Reset Value
0x00
Initial State
0
0
0
0
0
0
0
0
38-15