Esm Interrupt Enable Set/Status Register 1 (Esmiesr1); Esm Interrupt Enable Clear/Status Register 1 (Esmiecr1) - Texas Instruments TMS570LC4357 Technical Reference Manual

www.ti.com

16.4.3 ESM Interrupt Enable Set/Status Register 1 (ESMIESR1)

This register is dedicated for Group1 Channel[31:0].
Figure 16-13. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) [offset = 08h]
31
15
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-5. ESM Interrupt Enable Set/Status Register 1 (ESMIESR1) Field Descriptions
Bit Field
31-0 INTENSET

16.4.4 ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1)

This register is dedicated for Group1 Channel[31:0].
Figure 16-14. ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) [offset = 0Ch]
31
15
LEGEND: R/W = Read/Write; WP = Write in privileged mode only; -n = value after reset
Table 16-6. ESM Interrupt Enable Clear/Status Register 1 (ESMIECR1) Field Descriptions
Bit Field
31-0 INTENCLR
SPNU563A – March 2018
Submit Documentation Feedback
INTENSET[31:16]
INTENSET[15:0]
Value Description
Set interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding clear bit in the ESMIECR1 register unchanged.
1 Read: Interrupt is enabled.
Write: Enables interrupt and sets the corresponding clear bit in the ESMIECR1 register.
INTENCLR[31:16]
INTENCLR[15:0]
Value Description
Clear interrupt enable.
Read in User and Privileged mode. Write in Privileged mode only.
0 Read: Interrupt is disabled.
Write: Leaves the bit and the corresponding set bit in the ESMIESR1 register unchanged.
1 Read: Interrupt is enabled.
Write: Disables interrupt and clears the corresponding set bit in the ESMIESR1 register.
Copyright © 2018, Texas Instruments Incorporated
R/WP-0
R/WP-0
R/WP-0
R/WP-0
ESM Control Registers
Error Signaling Module (ESM)
16
0
16
0
567