Twi Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

Table A-20. UART1 Controller Registers (Cont'd)
Memory-Mapped
Address
0XFFC0 2024
0XFFC0 2028
0XFFC0 202C

TWI Registers

Two-Wire Interface (TWI) registers (0xFFC0 1400 – 0xFFC0 14FF) are
listed in Table
Table A-21. TWI Registers
Memory-Mapped
Address
0xFFC0 1400
0xFFC0 1404
0xFFC0 1408
0xFFC0 140C
0xFFC0 1410
0xFFC0 1414
0xFFC0 1418
0xFFC0 141C
ADSP-BF50x Blackfin Processor Hardware Reference
Register Name
UART1_IER_CLEAR
UART1_THR
UART1_RBR
A-21.
Register Name
TWI_CLKDIV
TWI_CONTROL
TWI_SLAVE_CTL
TWI_SLAVE_STAT
TWI_SLAVE_ADDR
TWI_MASTER_CTL
TWI_MASTER_STAT
TWI_MASTER_ADDR
System MMR Assignments
For individual bits, see this diagram:
"UARTx_IER_SET and UARTx_IER_CLEAR
Registers" on page 15-39
"UARTx_THR Registers" on page 15-37
"UARTx_RBR Registers" on page 15-38
For individual bits, see this diagram:
"SCL Clock Divider Register (TWI_CLK-
DIV)" on page 16-26
"TWI CONTROL Register (TWI_CON-
TROL)" on page 16-25
"TWI Slave Mode Control Register (TWI_
SLAVE_CTL)" on page 16-27
"TWI Slave Mode Status Register (TWI_
SLAVE_STAT)" on page 16-29
"TWI Slave Mode Address Register (TWI_
SLAVE_ADDR)" on page 16-29
"TWI Master Mode Control Register (TWI_
MASTER_CTL)" on page 16-31
"TWI Master Mode Status Register (TWI_
MASTER_STAT)" on page 16-35
"TWI Master Mode Address Register (TWI_
MASTER_ADDR)" on page 16-34
A-25