Can Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

CAN Registers

Table A-21. TWI Registers (Cont'd)
Memory-Mapped
Address
0xFFC0 1420
0xFFC0 1424
0xFFC0 1428
0xFFC0 142C
0xFFC0 1480
0xFFC0 1484
0xFFC0 1488
0xFFC0 148C
CAN Registers
Controller Area Network (CAN) registers (0xFFC0 2A00 –
0xFFC0 2FFF) are listed in
Table A-25.
Table A-22. CAN Mailbox Configuration 1 Registers
(For Mailboxes 0-15)
Memory-Mapped
Address
0XFFC0 2A00
0XFFC0 2A04
A-26
Register Name
TWI_INT_STAT
TWI_INT_MASK
TWI_FIFO_CTL
TWI_FIFO_STAT
TWI_XMT_DATA8
TWI_XMT_DATA16
TWI_RCV_DATA8
TWI_RCV_DATA16
Table
Register Name
CAN_MC1
CAN_MD1
ADSP-BF50x Blackfin Processor Hardware Reference
For individual bits, see this diagram:
"TWI Interrupt Status Register (TWI_INT_
STAT)" on page 16-43
"TWI Interrupt Mask Register (TWI_INT_
MASK)" on page 16-42
"TWI FIFO Control Register (TWI_FIFO_
CTL)" on page 16-38
"TWI FIFO Status Register (TWI_FIFO_
STAT)" on page 16-40
"TWI FIFO Transmit Data Single Byte Regis-
ter (TWI_XMT_DATA8)" on page 16-46
"TWI FIFO Transmit Data Double Byte Regis-
ter (TWI_XMT_DATA16)" on page 16-47
"TWI FIFO Receive Data Single Byte Register
(TWI_RCV_DATA8)" on page 16-48
"TWI FIFO Receive Data Double Byte Register
(TWI_RCV_DATA16)" on page 16-48
A-22, Table A-23,
For individual bits, see this diagram:
Mailbox config reg 1
Mailbox direction reg 1
Table A-24, and