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* If a register value is changed during operation, normal operation is not guaranteed. In this case, initialize
the register.
Table 3-3. Reception Trigger Level Settings (Bits 7 and 6 of FCR)
Bits 7 to 6 of
IIR
00
01
10
11
Table 3-4. DMA Mode Settings (Bit 3 of FCR and Bits 3 and 2 of HCR0)
Bit 3 of FCR
register
0
1
0
1
Others (Setting prohibited)
Table 3-5. DMA Modes and DMA Request Generation Conditions
Mode
When the DMA access data width is one byte (bit 5 of HCR0 = 0)
Receive DMA
Mode 0
request
Mode 1
Transmit DMA
Mode 0
request
Mode 1
When the DMA access data width is two bytes (bit 5 of HCR0 = 1).
Receive DMA
Mode 0
request
Mode 1
Transmit DMA
Mode 0
request
Mode 1
CHAPTER 3 REGISTERS
16-byte FIFO Mode
(Bit 5 of FCR Register = 0)
Trigger Level (Bytes)
01
04
08
14
Bits 3 and 2
Receive DMA Request
of HCR0
00
00
01
10
DMA Request Generation Condition
The receive FIFO stores 1 or more bytes of data. The receive FIFO is empty.
The amount of data in the receive FIFO
reached the trigger level or a timeout event
Note 1
occurred
.
The transmit FIFO is empty.
The transmit FIFO is empty.
The receive FIFO stores 2 or more bytes of data. The receive FIFO stores 1 or fewer bytes of
The trigger level is reached or a timeout event
Note 1
occurs
when the receive FIFO stores 2 or
more bytes of data.
The transmit FIFO is empty.
The transmit FIFO is empty.
User's Manual S19262EJ3V0UM
64-byte FIFO Mode
(Bit 5 of FCR Register = 1)
Trigger Level (Bytes)
01
16
32
56
Transmit DMA Request
Mode 0
Mode 1
Mode 0
Mode 1
DMA Request Release Condition
The receive FIFO is empty.
The transmit FIFO stores 1 or more bytes of
data.
The transmit FIFO is full.
Note 2
data
.
The receive FIFO stores 1 or fewer bytes of
Note 2
data
.
The transmit FIFO stores 2 or more bytes of
data.
The transmit FIFO full
Mode 1
Mode 0
19
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