Section 19 Clock Pulse Generator; Figure 19.1 Block Diagram Of Clock Pulse Generator - Renesas H8S/2111B Hardware Manual

This LSI incorporates a clock pulse generator, which generates the system clock (φ), bus master
clock, and internal clock.
The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit,
medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform
forming circuit. Figure 19.1 shows a block diagram of the clock pulse generator.
EXTAL
Oscillator
XTAL
Subclock
EXCL
input circuit

Figure 19.1 Block Diagram of Clock Pulse Generator

The bus master clock is selected as either high-speed mode or medium-speed mode by software
according to the settings of the SCK2 to SCK0 bits in the standby control register. For details on
the standby control register, refer to section 20.1.1, Standby Control Register (SBYCR).
The subclock input is controlled by software according to the EXCLE bit setting in the low power
control register. For details on the low power control register, refer to section 20.1.2, Low Power
Control Register (LPWRCR).

Section 19 Clock Pulse Generator

Duty
correction
circuit
Clock select
φSUB
Waveform
forming
circuit
WDT_1
count clock
Medium-
speed clock
divider
circuit
System clock
to φ pin
φ/2
to φ/32 Bus master
clock select
φ
circuit
Internal clock Bus master clock
to peripheral
modules
Rev. 1.00, 05/04, page 455 of 544
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