Instruction Register - Analog Devices ADSP-BF506F Hardware Reference Manual

Boundary-Scan Architecture
Note:
• The TAP controller enters the test-logic-reset state when
held high after five
• The TAP controller enters the test-logic-reset state when
asynchronously asserted.
• An external system reset does not affect the state of the TAP con-
troller, nor does the state of the TAP controller affect an external
system reset.

Instruction Register

The instruction register is five bits wide and accommodates up to 32
boundary-scan instructions.
The instruction register holds both public and private instructions. The
JTAG standard requires some of the public instructions; other public
instructions are optional. Private instructions are reserved for the manu-
facturer's use.
The binary decode column of
instructions. The register column lists the serial scan paths.
Table B-2. Decode for Public JTAG-Scan Instructions
Instruction Name
EXTEST
SAMPLE/PRELOAD
BYPASS
B-4
cycles.
TCK
Table B-2
Binary Decode
01234
00000
10000
11111
ADSP-BF50x Blackfin Processor Hardware Reference
lists the decode for the public
Register
Boundary-Scan
Boundary-Scan
Bypass
is
TMS
is
TRST