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Table A-28. PWM1 Registers
Memory-Mapped
Address
Motor Control PWM1 Registers (0xFFC03000 - 0xFFC030FF)
0XFFC0 3000
0XFFC0 3004
0XFFC0 3008
0XFFC0 300C
0XFFC0 3010
0XFFC0 3014
0XFFC0 3018
0XFFC0 301C
0XFFC0 3020
0XFFC0 3024
0XFFC0 3028
0XFFC0 302C
0XFFC0 3030
0XFFC0 3034
0XFFC0 3038
ADSP-BF50x Blackfin Processor Hardware Reference
Register Name
PWM1_CTRL
PWM1_STAT
PWM1_TM
PWM1_DT
PWM1_GATE
PWM1_CHA
PWM1_CHB
PWM1_CHC
PWM1_SEG
PWM1_SYNCWT
PWM1_CHAL
PWM1_CHBL
PWM1_CHCL
PWM1_LSI
PWM1_STAT2
System MMR Assignments
For individual bits, see this diagram:
PWM1 Control Register
PWM1 Status Register
PWM1 Period Register
PWM1 Dead Time Register
PWM1 Chopping Control
PWM1 Channel A Duty Control
PWM1 Channel B Duty Control
PWM1 Channel C Duty Control
PWM1 Crossover and Output Enable
PWM1 Sync pulse width control
PWM1 Channel AL Duty Control (SR mode
only)
PWM1 Channel BL Duty Control (SR mode
only)
PWM1 Channel CL Duty Control (SR mode
only)
Low Side Invert (SR mode only)
PWM1 Status Register
A-45
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