Operation - Analog Devices Linear LT3383 Demo Manual

Multioutput power management solution with 4 buck switching and 3 ldo linear regulators
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DEMO MANUAL DC2984A

OPERATION

Introduction to the DC2984A
The DC2984A a multi-output power management solu-
tion featuring the LT3383. It contains four synchronous
buck regulators and three LDO regulators. Among the
four buck regulators, BUCK1 and BUCK2 deliver up to
2.5A output current, while BUCK3 and BUCK4 deliver
up to 1.5A output current. All three LDOs deliver up to
300mA output current. BUCK1-BUCK4 have default out-
put voltages of 1.2V, 1.5V, 2.48V and 1.81V, respectively.
LDO1 and LDO2 have default output voltages of 1.2V and
0.8V respectively. These voltages are configured by volt-
age dividers on the corresponding FB pins and can be
changed by the user. LDO3 has a fixed voltage of 1.8V.
Power Up Sequencing
The LT3383 regulators can be powered up in any order by
pin-strapping outputs to enable pins. The enable pins have
a 0.75V (typical) input voltage threshold. If any enable is
driven high, the remaining enable input thresholds switch
to an 400mV threshold. There is a built-in 450µs delay
from the enable pin threshold crossing to the internal
enable of the regulator.
The DC2984A has a default power up sequence. User
can also program the power up sequence by selecting
JP4-JP10 to PGM/OFF position and connecting the out-
put rails to the enable pins at the Power Up Sequence
Programming Section shown in Figure 2. The start of the
sequence is the rising edge of the PWR_ON pin. PWR_ON
pin can be pulled up to VIN, pulled down to ground, or
connected to an external command source by selection
JP13, PWR_ON_CTRL jumper.
Figure 3 illustrates the output voltage of the buck regula-
tors when BUCK1-BUCK4 is programmed to start in an
ascending order. The demo board connection is shown
as follows:
SEQ_START -> EN_B1
VB1_SEQ -> EN_B2
VB2_SEQ -> EN_B3
VB3_SEQ -> EN_B4
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V
BUCK4
2V/DIV
V
BUCK3
2V/DIV
V
BUCK2
2V/DIV
V
BUCK1
2V/DIV
V
PWR_ON
5V/DIV
Figure 3. Program BUCK1-BUCK4 Power Up
Sequence in Ascending Order
Regulator Enables
When JP4-JP10 is at PGM/OFF position, and no connec-
tion is made at the Power Up Sequence Programming
Section, all the regulators are disabled. Each regulator can
be individually enabled by its corresponding enable turret.
LDO Input Selection
The default input of each LDO is the general input of the
demo circuit, VIN. To reduce power loss on the LDOs, the
input source of each LDO can be changed to the output
of BUCK3 by connection corresponding LDO
to V(B3). Each LDO can also be powered externally by
selecting the corresponding LDO
connecting a separate source to VIN_LDO
that the voltage of this external LDO source must not
exceed VIN voltage.
Power Good Indicator
Power Good LED D2 is turned on when PGOOD pin on
LT3383 is pulled low. It indicates one or multiple output
voltages of the enabled regulators are low. It is also on
when no regulator is enabled.
DC2984A F03
1ms/DIV
VIN jumper
X
VIN jumper to EXT and
X
turret. Note
X
Rev. 0

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