Frame Sync Error Detection - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

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Frame Sync Options

mode of operation allows data to be transmitted only at specific times.

only when receive data buffer status is not full.

sync is output at its programmed interval regardless of whether new data is

available in the transmit buffer. The processor generates the transmit

signal at the frequency specified by the value loaded in the

registers. If a frame sync occurs when the transmitter FIFO is empty, the

MSB or LSB (depending on how the

ous word is transmitted. When

signal is generated regardless of the receive data buffer status.

Depending on the SPORT operating mode, the transmitter underflow

when a frame sync occurs; or a receive overflow bit (

set if the receive buffers are full and a new data word is received.

If the internally-generated frame sync is used and

the transmit data register is required to start the transfer.

Frame Sync Error Detection

Similar to the SPORTs on previous SHARC processors, the SPORTs can

detect underflow and overflow errors. In addition to this, the SPORTs on

the ADSP-21367/8/9 and ADSP-2137x processors can also detect frame

syncs that are occurring early, even before the last transmit or receive

To detect these errors, these processors have a new error interrupt that

works for all eight SPORTs together. It is triggered on a data underflow,

data overflow, or frame sync error in their respective channels.

= 0, a receive

= 1, the internally-generated transmit frame

) bit is set if the transmit buffer does not have new data

ADSP-21368 SHARC Processor Hardware Reference

signal is generated

= 0, a receive

=0, a single write to

is set) of the previ-