Extra Cycle Conditions; Multiple Off-Chip Memory Accesses; Wait States; Sport Autobuffering & Dma - Analog Devices adsp-2100 Manual

15 Instruction Set Reference
15.9
All instructions execute in a single cycle except under certain conditions,
as explained below.
15.9.1
The data and address busses of the ADSP-21xx processors are multiplexed
off-chip. Because of this, the processors can perform only one off-chip
access per instruction in a single cycle. If two off-chip accesses are
required—the instruction fetch and one data fetch, for example, or data
fetches from both program and data memory—then one overhead cycle
occurs. In this case the program memory access occurs first, then the data
memory access. If three off-chip accesses are required—the instruction
fetch as well as data fetches from both program and data memory—then
two overhead cycles occur.
A multifunction instruction requires three items to be fetched from
memory: the instruction itself and two data words. No extra cycle is
needed to execute the instruction as long as only one of the fetches is from
external memory. (Two fetches must be from on-chip memory, either PM
or DM.)
15.9.2
All family processors allow the programming of wait states for external
memory chips. Up to seven extra wait state cycles may be added to the
processor's access time for external memory. Extra cycles inserted due to
wait states are in addition to any caused by multiple off-chip accesses (as
described above). Wait state programming is described in the "Memory
Interface" chapter.
Wait states and multiple off-chip memory accesses are the two cases when
an extra cycle is generated during instruction execution. The following
case, SPORT autobuffering and DMA, causes the insertion of extra cycles
between instructions.
15.9.3
If serial port autobuffering or ADSP-2181 DMA is being used to transfer
data words to or from internal memory, then one memory access is
"stolen" for each transfer. The stolen memory access occurs only between
complete instructions. If extra cycles are required to execute any
instruction (for one of the two reasons above), the processor waits until it
is completed before "stealing" the access cycle.
15 –18

EXTRA CYCLE CONDITIONS

Multiple Off-Chip Memory Accesses

Wait States

SPORT Autobuffering & DMA