Analog Devices ADSP-BF506F Hardware Reference Manual page 1283

Adsp-bf50x blackfin processor
Hide thumbs Also See for ADSP-BF506F:
Table of Contents

Advertisement

general-purpose timers
non-overlapping clock pulses,
output pad disable,
10-12
overflow,
10-4
periodic interrupt requests,
port setup,
10-49
and PPI,
10-58
preventing errors in PWM_OUT mode,
10-45
programming model,
PULSE_HI toggle mode,
PWM mode,
10-5
PWM_OUT mode,
10-44
registers,
10-35
signal generation,
10-50
single pulse generation,
size of register accesses,
stopping in PWM_OUT mode,
three timers with same period,
two timers with non-overlapping clocks,
10-18
waveform generation,
WDTH_CAP mode, 10-24,
WDTH_CAP mode configuration,
10-56
WDTH_CAP mode flow diagram,
10-24
GEN (general call enable) bit, 16-27,
GIRQ bit,
17-46
glitch filtering, UART,
global interrupts, CAN,
global interrupt status register (CAN_GIS),
17-47
global status register (CAN_STATUS),
17-44
GM (get more data) bit, 18-21,
GPIO, 1-9,
9-1
to
9-42
assigned to same interrupt channel,
clearing interrupt conditions,
ADSP-BF50x Blackfin Processor Hardware Reference
(continued)
10-54
10-52
10-34
10-16
10-10
to 10-23,
10-13
10-36
10-22
10-18
10-14
10-44
16-28
15-14
17-23
18-37
9-21
9-18
GPIO
clear registers,
9-15
code examples,
9-41
configuration,
9-13
data registers, 9-13, 9-14,
direction registers, 9-13,
edge detection,
9-17
edge-sensitive,
9-15
flow chart,
9-22
function enable registers, 9-12, 9-13,
9-16
input buffers,
9-14
input driver,
9-14
input drivers,
9-18
input enable registers, 9-14,
interrupt channels,
9-21
interrupt generation flow chart,
interrupt request,
4-14
interrupts,
9-17
interrupt sensitivity registers,
mask data registers,
9-19
mask interrupt clear registers,
mask interrupt set registers,
mask interrupt toggle registers,
mask registers,
9-18
overview,
1-9
pins, 9-12,
9-13
polarity registers,
9-17
registers,
9-27
set registers,
9-15
toggle registers,
9-16
using as input,
9-14
write operations,
9-14
writes to registers,
9-15
GPIO clear (PORTxIO_CLEAR) registers,
9-32
GPIO data (PORTxIO) registers,
GPIO direction (PORTxIO_DIR)
registers, 9-30, 14-41, 14-42, 14-44,
14-47, 14-48, 14-49,
Index
(continued)
9-15
9-18
9-16
9-19
9-17
9-20
9-20
9-20
9-31
14-50
I-19

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ADSP-BF506F and is the answer not in the manual?

This manual is also suitable for:

Adsp-bf504Adsp-bf504f

Table of Contents