Analog Devices ADSP-BF506F Hardware Reference Manual page 1292

Index
period value[15:0] field,
period value[31:16] field,
peripheral
DMA, 7-5
DMA channels, 7-42
DMA transfers, 7-2
error interrupts, 7-73
interrupt request lines,
supporting interrupts,
peripheral access bus. See PAB
Peripheral bus
errors generated by SPORT,
peripheral DMA start address registers,
7-75
peripheral interrupts, 4-2, 4-3,
peripheral map registers
(DMAx_PERIPHERAL_MAP),
(MDMA_yy_PERIPHERAL_MAP),
7-67
peripheral pins, default configuration,
peripherals, 1-4
and buses, 1-4
compatible with SPI,
and DMA controller,
DMA support, 1-4
enabling, 9-3
interrupt generated by,
interrupts, clearing, 4-13
level-sensitivity of interrupts,
list of, 1-4
mapping to DMA, 7-105
multiplexing, 9-1
remapping DMA assignment,
switching from DMA to non-DMA,
7-75
timing, 3-4
used to wake from idle,
PF0 pin, 9-15
PFx pin, 18-7
phase locked loop. See PLL
I-28
11-6
11-6
4-15
4-1
19-39
4-4 to 4-7
7-67
9-13
18-3
7-32
4-8
4-15
7-6
4-6
ADSP-BF50x Blackfin Processor Hardware Reference
pin information, 25-1
pins, 25-1
GPIO, 9-12
multiplexing, 9-1
unused, 25-10
pin terminations, SPORT,
pipeline, lengths of, 7-52
pipelining
DMA requests, 7-38
PJSE bit, 9-27, 9-28, 9-29
PLL, 8-1 to 8-29
active (enabled but bypassed) mode,
active mode, 8-9
applying power to the PLL,
block diagram, 8-4
BYPASS bit, 8-9
CCLK derivation, 8-4
changing clock ratio,
clock control, 8-1
clock dividers, 8-4
clock multiplier ratios,
configuration, 8-3
control bits, 8-11
deep sleep mode, 8-10
design overview, 8-2
disabled, 8-13
divide frequency, 8-4
DMA access, 8-9
dynamic power management controller
(DPMC), 8-7
enabled, 8-13
hibernate state, 8-11
interacting with DPMC,
and internal clocks, 3-2
maximum performance mode,
modification in active mode,
multiplier select (MSEL) field,
operating modes, operational
characteristics, 8-8
operating mode transitions, 8-11,
19-9
8-9
8-13
8-6
8-4
8-2
8-8
8-13
8-4
8-13