Analog Devices ADSP-BF506F Hardware Reference Manual page 1278

Index
DMA
stop mode, 7-11, 7-69
stopping transfers, 7-29
support for peripherals,
switching peripherals from,
and synchronization with PPI,
synchronization, 7-51
synchronized transition,
termination without abort,
throughput, 7-42
traffic control, 7-49
traffic exceeding available bandwidth,
7-46
transfers, 1-8, 3-11
transfers, urgent, 7-45
transmit, 7-26
transmit restart or finish, 7-35,
triggering transfers, 7-61
two descriptors in small list flow mode,
example, 7-96
two-dimensional, 7-11
two-dimensional memory DMA setup
example, 7-94
types supported, 1-8
and UART, 15-24, 15-39
using descriptor structures example,
variable descriptor size,
with PPI, 20-22
word size, changing, 7-28,
work units, 7-14, 7-23,
DMA2D bit, 7-68, 7-71
DMA bus. See DAB
DMACFG field, 7-21,
DMA channel registers,
DMACODE field, 24-13,
DMA Code field
DMACODE, 24-13
DMA configuration (DMAx_CONFIG)
registers, 7-68
I-14
(continued)
1-4
7-75
20-13
to 7-61
7-28
7-29
7-36
7-97
7-15
7-29
7-25
7-63
7-64
24-73
ADSP-BF50x Blackfin Processor Hardware Reference
DMA configuration
(MDMA_yy_CONFIG) registers,
7-68
DMA controller, 7-2
DMA core bus. See DCB
DMA direction (WNR) bit, 7-68,
DMA_DONE bit, 7-10,
DMA_DONE interrupt,
DMAEN bit, 7-18, 7-62, 7-68,
DMA_ERR bit, 7-10,
DMA_ERROR interrupt,
DMA error interrupts,
DMA external bus. See DEB
DMA performance optimization,
DMA queue completion interrupt,
DMA registers, 7-63, 7-64
DMA_RUN bit, 7-22, 7-59, 7-62, 7-72,
7-74
DMA_RUN bit), 7-10
DMARx pin, 7-38
DMA start address field,
DMA_TC_CNT (DMA traffic control
counter) register, 7-90,
DMA_TC_PER (DMA traffic control
counter period) register, 7-47,
DMA traffic control registers,
DMA_TRAFFIC_PERIOD field,
DMAx_CONFIG (DMA configuration)
registers, 7-8, 7-18, 7-25,
DMAx_CURR_ADDR (current address)
registers, 7-76
DMAx_CURR_DESC_PTR (current
descriptor pointer) registers,
DMAx_CURR_X_COUNT (current
inner loop count) registers,
DMAx_CURR_Y_COUNT (current
outer loop count) registers,
DMAx_IRQ_STATUS (interrupt status)
registers, 7-72, 7-74
7-71
7-74
7-72
7-71
7-74
7-30
7-73
7-41
7-60
7-75
7-91
7-91
7-89
7-91
7-68
7-82
7-77
7-80