Analog Devices ADSP-BF506F Hardware Reference Manual page 1306

Index
TWI
features, 16-2
general call address, 16-10
general setup, 16-11
2
I C compatibility, 1-10
master mode clock setup,
master mode receive,
master mode transmit,
peripheral interface,
pins, 16-5
slave mode operation,
start and stop conditions,
synchronization, 16-7
transfer protocol, 16-6
TWI_CLKDIV (SCL clock divider)
register, 16-26, 16-27
TWI_CONTROL (TWI control) register,
16-4, 16-26
TWI_ENA bit, 16-26
TWI_FIFO_CTL (TWI FIFO control)
register, 16-38
TWI_FIFO_STAT (TWI FIFO status)
register, 16-40
TWI_INT_STAT (TWI interrupt status)
register, 16-43
TWI_MASTER_CTL (TWI master mode
control) register, 16-31
TWI_MASTER_STAT (TWI master
mode status) register,
TWI_SLAVE_ADDR (TWI slave mode
address) register, 16-29
TWI_SLAVE_CTL (TWI slave mode
control) register, 16-27
TWI_SLAVE_STAT (TWI slave mode
status) register, 16-30
two-dimensional DMA,
two-wire interface. See TWI
TXCOL flag, 18-42
TXCOL (transmit collision error) bit,
18-40
I-42
(continued)
16-12
16-14
16-13
16-5
16-11
16-8
16-35
7-11
ADSP-BF50x Blackfin Processor Hardware Reference
TXECNT[7:0] field, 17-84
TXE (transmission error) bit, 18-40, 18-42,
19-58, 19-63
TXF (transmit FIFO full status) bit,
TX hold register, 19-57
TXHRE (transmit hold register empty) bit,
19-63
TXREQ signal, 15-7
TXSE (TxSEC enable) bit, 19-49,
TXS (SPI_TDBR data buffer status) bit,
18-23, 18-40
U
UART, 1-19, 15-1 to 15-55
autobaud detection, 15-20,
baud rate, 15-8
baud rate examples,
bit rate examples, 15-19
bitstream, 15-6
block diagram, 15-3,
booting, 15-20
character transmission,
clock, 15-18
clock rate, 3-4
code examples, 15-46
data words, 15-6
divisor reset, 15-44
DMA channels, 15-24
DMA mode, 15-24
errors during reception,
external interfaces, 15-3
features, 15-2
glitch filtering, 15-14
initialization, 15-47
internal interfaces, 15-5
interrupt channels, 15-39
interrupt conditions,
interrupts, 15-16
IrDA mode, 15-2
IrDA receiver, 15-14
19-62
19-52
15-50
15-19
15-11
15-50
15-9
15-42