Analog Devices ADSP-BF506F Hardware Reference Manual page 1289

MCOMP (master transfer complete) bit,
16-43, 16-44
MCOMPM (master transfer complete
interrupt mask) bit,
MCx bit, 17-68
MDIR (master transfer direction) bit,
16-31, 16-33
MDMA channels, 7-6
MDMA controllers, 7-6
MDMA_ROUND_ROBIN_COUNT[4:
0] field, 7-48, 7-91
MDMA_ROUND_ROBIN_PERIOD
field, 7-47, 7-48,
MDMA_yy_CONFIG (DMA
configuration) registers,
MDMA_yy_CURR_ADDR (current
address) registers,
MDMA_yy_CURR_DESC_PTR (current
descriptor pointer) registers,
MDMA_yy_CURR_X_COUNT (current
inner loop count) registers,
MDMA_yy_CURR_Y_COUNT (current
outer loop count) registers,
MDMA_yy_IRQ_STATUS (interrupt
status) registers, 7-72,
MDMA_yy_NEXT_DESC_PTR (next
descriptor pointer) registers,
MDMA_yy_PERIPHERAL_MAP
(peripheral map) registers,
MDMA_yy_START_ADDR (start
address) registers,
MDMA_yy_X_COUNT (inner loop
count) registers, 7-76
MDMA_yy_X_MODIFY (inner loop
address increment) registers,
MDMA_yy_Y_COUNT (outer loop
count) registers, 7-79
MDMA_yy_Y_MODIFY (outer loop
address increment) registers,
MDn bit, 17-69
ADSP-BF50x Blackfin Processor Hardware Reference
16-42
7-91
7-68
7-76
7-82
7-77
7-80
7-74
7-81
7-67
7-75
7-78
7-80
measurement report, general-purpose
timers, 10-25, 10-27,
memory, 2-1 to 2-6
accesses to internal, 2-1
architecture, 1-4, 2-1
boot ROM, 2-4
configurations, 1-5
external, 1-6, 2-4
flash, 1-6
Flash memory region,
internal, 1-6
internal interfaces, 5-4
L1, 3-4
L1 data, 1-6, 2-3
L1 data cache, 2-4
L1 instruction, 1-6,
L1 scratchpad RAM,
moving data between SPORT and,
19-38
off-chip, 1-5, 1-6
on-chip, 1-5, 1-6
OTP, 1-7
start locations of L1 instruction memory
subbanks, 2-3
structure, 1-4
unpopulated, 5-6
memory conflict, DMA,
memory DMA, 1-8, 7-6
bandwidth, 7-44
buffers, 7-8
channels, 7-7
descriptor structures,
handshake operation,
priority, 7-47
scheduling, 7-47
timing, 7-45
transfer operation, starting,
transfer performance,
transfers, 7-2, 7-5
word size, 7-7
Index
10-28
5-3
2-2
1-6
7-49
7-63
7-8
7-8
3-11
I-25