Analog Devices ADSP-BF506F Hardware Reference Manual page 1305

TMODE[1:0] field, 10-11, 10-42,
TMPWR bit, 11-3, 11-5
TMRCLK input, 10-58
TMREN bit, 11-3, 11-5
TMR pin, 10-47
TMRx pins, 10-3, 10-16
TOGGLE_HI bit, 10-42,
TOGGLE_HI mode, 10-17
toggle Pxn bit, 9-33
toggle Pxn interrupt A enable bit,
toggle Pxn interrupt B enable bit,
tools, development, 1-28
TOVF_ERRx bit, 10-25,
TOVF_ERRx bits, 10-4, 10-7, 10-15,
10-40, 10-41, 10-48
TOVF (transmit overflow status) bit,
19-58, 19-62, 19-63
TPOLC bit, 15-45, 15-46
traffic control, DMA, 7-45
transfer count (PPI_COUNT) register,
20-32, 20-33
transfer initiate command, 18-18,
transfer initiation from SPI master,
transfer rate
memory DMA channels,
peripheral DMA channels,
transfers
memory-to-memory,
transitions
continuous DMA, 7-25
DMA work unit, 7-25
operating mode, 8-11,
synchronized DMA,
transmission acknowledge register 1
(CAN_TA1), 17-76
transmission acknowledge register 2
(CAN_TA2), 17-76
transmission error, SPI,
transmission request reset register 1
(CAN_TRR1), 17-74
ADSP-BF50x Blackfin Processor Hardware Reference
10-46
10-47
9-40
9-41
10-29
to 7-50
18-19
18-19
7-42
7-42
7-7
8-12
7-25
18-42
transmission request reset register 2
(CAN_TRR2), 17-74
transmission request set register 1
(CAN_TRS1), 17-73
transmission request set register 2
(CAN_TRS2), 17-73
transmit clock, serial (TSCLKx) pins,
19-30
transmit collision error, SPI,
transmit configuration registers
(SPORTx_TCR1 and
SPORTx_TCR2),
transmit data[15:0] field,
transmit data[31:16] field,
transmit data buffer[15:0] field,
transmit hold[7:0] field, 15-37,
TRFST (left/right order) bit, 19-49,
triggering DMA transfers,
TRM bit, 17-44
TRRn bit, 17-74
TRSn bit, 17-73
TRUNx bits, 10-22, 10-39, 10-40,
TSCALE (core timer scale) register, 11-3,
11-7
TSCLKx signal, 19-5
TSEG1[3:0] field, 17-10,
TSEG2[2:0] field, 17-10,
TSFSE (transmit stereo frame sync enable)
bit, 19-10, 19-11, 19-49,
TSPEN (transmit enable) bit, 19-47,
19-48, 19-49
TUVF (transmit underflow status) bit,
19-37, 19-58, 19-62,
TWI, 1-10, 16-2 to 16-61
block diagram, 16-3
bus arbitration, 16-8
clock generation, 16-7
controller, 16-2
electrical specifications,
fast mode, 16-10
Index
18-42
19-47
19-59
19-59
18-43
15-38
19-52
7-61
10-48
17-46
17-46
19-52
19-63
16-61
I-41