Analog Devices ADSP-BF506F Hardware Reference Manual page 1279

DMAx_NEXT_DESC_PTR (next
descriptor pointer) registers, 7-17,
7-81
DMAx_PERIPHERAL_MAP (peripheral
map) registers, 4-6,
DMAx_START_ADDR (start address)
registers, 7-17, 7-75
DMAx_X_COUNT (inner loop count)
registers, 7-76
DMAx_X_MODIFY (inner loop address
increment) registers, 7-18,
DMAx_Y_COUNT (outer loop count)
registers, 7-79
DMAx_Y_MODIFY (outer loop address
increment) registers, 7-18,
DMC[1:0] field, 2-5
DMEM_CONTROL (data memory
control) register, 2-4,
DNAK (data not acknowledged) bit,
16-35, 16-37
DNM bit, 17-43
DOUBLE_FAULT bit,
double word index[1:0] field,
DPMC, 8-2, 8-7 to 8-19
DR bit, 15-17
DR (data ready) bit, 15-33,
DR flag, 15-23
DRI bit, 17-35, 17-45
DRQ[1:0] field, 7-46, 7-84,
DRxPRI signal, 19-5
DRxPRI SPORT input,
DRxSEC signal, 19-5
DRxSEC SPORT input,
DTEST_COMMAND (data test
command) register,
DTO bit, 17-35, 17-45
DTxPRI signal, 19-5
DTxPRI SPORT output,
DTxSEC signal, 19-5
DTxSEC SPORT output,
ADSP-BF50x Blackfin Processor Hardware Reference
7-67
7-78
7-80
2-5
24-60
2-6
15-34
7-85
19-6
19-6
2-6
19-6
19-6
dynamic power management, 1-24,
controller, 8-2
E
EAB
arbitration, 3-10
and EBIU, 5-4
frequency, 3-10
performance, 3-10
early frame sync, 19-35
EAV signal, 20-5
EBC, 5-4
EBIU, 1-6, 5-1 to 5-12
as slave, 5-4
block diagram, 5-3
bus errors, 5-5
clock, 5-1
clocking, 8-2
control registers, 5-4
and DMA, 7-4
error detection, 5-5
overview, 5-1
request priority, 5-1
status register, 5-4
EBIU_AMBCTL (asynchronous memory
bank control) register,
EBIU_AMGCTL (asynchronous memory
global control) register,
EBIU chapter, 5-1
EBIU_FCTL (asynchronous Flash memory
parameter control) register,
EBIU_MODECTL (asynchronous
memory mode control) register,
EBO bit, 17-44
ECINIT[15:0] field, 7-88
ECOM (events completed) bit,
ECOUNT[15:0] field,
edge detection, GPIO,
elfloader.exe, 24-9
ELSI bit, 15-9, 15-40, 15-41,
Index
8-1
5-11
5-10
5-12
5-12
22-33
7-88
9-17
15-42
I-15