Table of Contents
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BUFRDERR (buffer read error) bit, 16-35,
16-37
BUFWRERR (buffer write error) bit,
16-35,
16-37
bus agents
DAB,
3-9
PAB,
3-6
BUSBUSY (bus busy) bit, 16-35,
bus contention, avoiding,
bus error, EBIU,
5-5
buses
See also DAB, DCB, DEB, EAB, EPB,
PAB
bandwidth,
1-4
core,
3-4
hierarchy,
3-2
on-chip,
3-1
PAB,
3-5
peripheral,
3-5
and peripherals,
1-4
prioritization and DMA,
bus-off interrupt, CAN,
2
bus standard, I
C,
1-10
bypass
capacitor placement,
BYPASS bit,
8-21
BYPASS instruction,
B-6
BYPASS register,
B-6
C
callback routines,
24-30
CAN, 1-21,
17-1
to
17-91
abort acknowledge interrupt,
acceptance mask filtering,
acceptance mask registers,
access denied interrupt,
access to unimplemented address
interrupt,
17-25
acknowledge error,
17-28
architecture,
17-4
ADSP-BF50x Blackfin Processor Hardware Reference
16-36
5-6
7-49
17-25
25-7
17-25
17-16
17-6
17-24
CAN
auto-transmit mode,
bit error,
17-28
bit timing,
17-10
block diagram,
17-3
bus interface,
17-2
bus-off interrupt,
17-25
clock,
17-10
code examples,
17-85
configuration mode, 17-9,
CRC error,
17-29
data field filtering,
17-18
debug and test modes,
enabling mailboxes,
error frames, 17-26,
error levels,
17-31
errors,
17-27
error warning receive interrupt,
error warning transmit interrupt,
event counter,
17-26
extended frame,
17-9
external trigger output interrupt,
features,
17-1
form error,
17-28
global interrupts, 17-21,
hibernate state,
17-38
identifier frame,
17-8
initializing code,
17-85
initializing mailboxes,
initiating transfers,
17-88
interrupt processing,
interrupts,
17-22
lost arbitration,
17-26
low power designs,
17-38
low power features,
17-37
mailbox area registers,
mailbox control,
17-6
mailboxes,
17-4
mailbox interrupts,
17-23
mailbox RAM,
17-4
Index
(continued)
17-15
17-12
17-33
17-87
17-29
17-26
17-26
17-24
17-23
17-87
17-88
17-5
I-5
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