Analog Devices ADSP-BF506F Hardware Reference Manual page 1290

Index
memory map
ADSP-BF50x, 2-2
memory map, external (figure),
memory-mapped registers. See MMRs
memory-to-memory transfers,
MEN (master mode enable) bit, 16-31,
16-33
MERR (master transfer error) bit, 16-43,
16-44
MERRM (master transfer error interrupt
mask) bit, 16-42
MFD[3:0] field, 19-21,
MIEx (event x missed interrupt enable)
bits, 22-37
MINCIE (min count interrupt enable) bit,
13-20
MINCII (min count interrupt identifier)
bit, 13-21
min count interrupt identifier (MINCII)
bit, 13-21
minimal count (CNT_MIN) register,
13-19, 13-25
minimum count interrupt enable
(MINCIE) bit, 13-20
MISO pin, 18-5, 18-12, 18-15, 18-16,
18-21
MMRs, 1-7
address range, A-2
for PPI, 20-25
memory-related, 2-5
width, A-2
mode fault error, 18-17,
modes
broadcast, 18-9, 18-15,
multichannel, 19-15
serial port, 19-11
SPI master, 18-15, 18-18
SPI slave, 18-16, 18-20
UART DMA, 15-24
UART non-DMA, 15-22
I-26
5-2
7-7
19-66
18-41
18-16
ADSP-BF50x Blackfin Processor Hardware Reference
MODF (mode fault error) bit, 18-40,
18-41
MOSI pin, 18-5, 18-12, 18-15, 18-16,
18-21
moving data, serial port,
MPROG (master transfer in progress) bit,
16-35, 16-38
MRB bit, 17-45
MRTS (manual request to send) bit,
MSEL[5:0] field, 8-4, 8-21
MSTR (master) bit, 18-36,
multichannel frame, 19-20
multichannel frame delay field,
multichannel mode, 19-15
enable/disable, 19-18
frame syncs, 19-19
SPORT, 19-19
multichannel operation, SPORT,
19-25
multiple interrupt sources,
multiple slave SPI systems,
multiplexing, 9-1
MVIP-90, 19-25
N
NAK (not acknowledge) bit, 16-27,
NDPH bit, 7-21
NDPL bit, 7-21
NDSIZE[3:0] field, 7-15, 7-68,
legal values, 7-32
next descriptor pointer registers
(DMAx_NEXT_DESC_PTR),
(MDMA_yy_NEXT_DESC_PTR),
7-81
nFlags variable, 24-72
nominal bit rate, CAN,
nominal bit time, CAN,
normal frame sync mode,
normal timing, serial port,
NTSC systems, 20-6
19-38
15-31
18-37
19-21
19-15 to
4-9
18-8
16-28
7-70
7-81
17-11
17-10
19-35
19-35