Analog Devices ADSP-BF506F Hardware Reference Manual page 1302

Index
SPORTx_CHNL (SPORTx current
channel) registers,
SPORTx_MCMCn (SPORTx
multichannel configuration) registers,
19-65
SPORTx_MRCSn (SPORTx
multichannel receive select) registers,
19-23, 19-24, 19-67
SPORTx_MTCSn (SPORTx
multichannel transmit select) registers,
19-23, 19-24, 19-68
SPORTx_RCLKDIV (SPORTx receive
serial clock divider) registers,
SPORTx_RCR1 (SPORTx receive
configuration 1) registers,
SPORTx_RCR2 (SPORTx receive
configuration 2) registers, 19-52,
19-54
SPORTx_RFSDIV (SPORTx receive
frame sync divider) registers,
SPORTx_RX (SPORTx receive data)
registers, 19-19, 19-59
SPORTx_STAT (SPORTx status)
registers, 19-62
SPORTx_TCLKDIV (SPORTx transmit
serial clock divider) registers,
SPORTx_TCR1 (transmit configuration
1) register, 19-47
SPORTx_TCR2 (transmit configuration
2) register, 19-47
SPORTx_TFSDIV (SPORTx transmit
frame sync divider) registers,
SPORTx_TX (SPORTx transmit data)
registers, 19-19, 19-37,
SRAM ADDR[13:12] field,
SRS bit, 17-43
SSEL[3:0] field, 3-4, 8-5,
SSEL bit, 25-2
SSEL (system select) bit,
I-38
19-66
19-63
19-52
19-64
19-63
19-64
19-57
2-6
8-20
8-20
ADSP-BF50x Blackfin Processor Hardware Reference
start address registers
(DMAx_START_ADDR),
(MDMA_yy_START_ADDR),
status (CNT_STATUS) register, 13-18,
13-21
STB (stop bits) bit, 15-28
STDVAL (slave transmit data valid) bit,
16-27, 16-28
stereo serial
data, 19-3
device, SPORT connection,
frame sync modes, 19-18
operation, SPORT, 19-11
STOPCK (stop clock) bit,
stop clock (STOPCK) bit,
STOP (issue stop condition) bit,
stop mode, DMA, 7-11,
stopping DMA transfers,
STP (stick parity) bit, 15-28
streams, memory DMA,
subbank access[1:0] field,
subbanks
L1 data memory, 2-3
L1 instruction memory,
supervisor mode, 24-8
surface-mount capacitors,
suspend mode, CAN, 17-37
SWRESET bit, 24-61
SWRST, software reset register,
SWRST (software reset register),
SYNC bit, 7-25, 7-26, 7-27, 7-62, 7-68,
7-70, 15-24
synchronization
interrupt-based methods,
of descriptor queue,
of DMA, 7-51 to 7-61
synchronized transition, DMA,
synchronous Flash memory controller. See
Flash memory controller
synchronous serial data transfer,
7-75
7-75
19-9
8-21
8-21
16-33
7-69
7-29
7-7
2-6
2-3
25-6
24-59
24-60
7-51
7-58
7-28
19-4