Analog Devices ADSP-BF506F Hardware Reference Manual page 1288

Index
LOOPBACK (loopback mode enable) bit,
15-31
loopback mode, UART,
LOSTARB (lost arbitration) bit, 16-35,
16-38
LRFS (low receive frame sync select) bit,
19-13, 19-32, 19-33, 19-53,
LSBF (LSB first) bit, 18-37
LT_ERR_OVR flag, 20-31
LT_ERR_OVR (horizontal tracking
overflow error) bit, 20-30,
LT_ERR_UNDR flag,
LT_ERR_UNDR (horizontal tracking
underflow error) bit, 20-30,
LTFS (low transmit frame sync select) bit,
19-20, 19-32, 19-33, 19-48,
M
MAA bit, 17-45
MADDR[6:0] field, 16-34
mailbox configuration register 1
(CAN_MC1), 17-68
mailbox configuration register 2
(CAN_MC2), 17-68
mailbox direction register 1 (CAN_MD1),
17-69
mailbox direction register 2 (CAN_MD2),
17-69
mailboxes, CAN, 17-4
mailbox interrupt mask registers,
mailbox interrupts, CAN,
mailbox receive interrupt flag registers,
17-80
mailbox transmit interrupt flag registers,
17-79
mailbox word 0 register
(CAN_MBxx_DATA0),
mailbox word 1 register
(CAN_MBxx_DATA1),
I-24
15-31
19-56
20-31
20-31
20-31
19-51
17-78
17-23
17-66
17-64
ADSP-BF50x Blackfin Processor Hardware Reference
mailbox word 2 register
(CAN_MBxx_DATA2),
mailbox word 3 register
(CAN_MBxx_DATA3),
mailbox word 4 register
(CAN_MBxx_LENGTH),
mailbox word 6 register
(CAN_MBxx_ID0), 17-54,
mailbox word 7 register
(CAN_MBxx_ID1),
master control register
(CAN_CONTROL),
masters
DAB, 3-9
PAB, 3-6
MAXCIE (max count interrupt enable) bit,
13-20
MAXCII (max count interrupt identifier)
bit, 13-21
max count interrupt identifier (MAXCII)
bit, 13-21
maximal count (CNT_MAX) register,
13-19, 13-25
maximum count interrupt enable
(MAXCIE) bit, 13-20
MBDI bit, 7-41, 7-85
MBIMn bit, 17-78, 17-79
MBPTR[4:0] field, 17-44
MBRIFn bit, 17-80, 17-81
MBRIRQ bit, 17-46
MBTIFn bit, 17-79, 17-80
MBTIRQ bit, 17-46
MCCRM[1:0] field, 19-66
MCDRXPE (multichannel DMA receive
packing) bit, 19-66
MCDTXPE (multichannel DMA transmit
packing) bit, 19-66
MCMEN (multichannel frame mode
enable) bit, 19-18,
17-62
17-59
17-58
17-56
17-52
17-43
19-66