Figure B-2
shows the instruction bit scan ordering for the paths shown in
Table
B-2.
N
TDI
0
Figure B-2. Serial Scan Paths
ADSP-BF50x Blackfin Processor Hardware Reference
Boundary-Scan Register
N-2
N-1
Bypass Register
1
31
30
1
2
JTAG Instruction Register
2
1
0
TDO
0
1
4
3
Test Features
B-5
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