Analog Devices ADSP-BF506F Hardware Reference Manual page 1293

PDWN bit, 8-11
PLL_OFF bit, 8-13
PLL status (table), 8-8
power domains, 8-16
power savings by operating mode (table),
8-8
registers, table, 8-20
removing power to the PLL,
SCLK derivation, 8-1,
sleep mode, 8-9
STOPCK bit, 8-11
voltage control, 8-7
PLL control (PLL_CTL) register, 8-4, 8-5,
8-20, 8-21
PLL_CTL (PLL control) register, 8-4, 8-5,
8-20, 8-21
PLL divide register, 3-4
PLL_DIV (PLL divide) register, 8-6,
PLL_LOCKCNT (PLL lock count)
register, 8-20, 8-22
PLL_LOCKED bit, 8-21
PLL_OFF bit, 8-21
PLL_STAT (PLL status) register, 8-20,
8-21
PMAP[3:0] field, 7-5, 7-45,
polarity, GPIO, 9-17
POLC (polarity change) bit, 20-4, 20-25,
20-26
polling DMA registers,
POLS bit, 20-4, 20-25,
PORT_CFG[1:0] field, 20-4, 20-26,
20-28
port connection, SPORT,
PORT_DIR bit, 13-25
PORT_DIR (direction) bit, 20-4, 20-26,
20-28
PORT_EN (enable) bit, 20-26,
ADSP-BF50x Blackfin Processor Hardware Reference
8-13
8-4
8-20
7-67
7-52
20-26
19-7
20-29
port F
GPIO, 9-13
peripherals, 9-1
structure, 9-3
PORTF_FER (function enable) register,
9-10
PORTF_HYSTERESIS register,
port G
GPIO, 9-13
peripherals, 9-2, 9-5
structure, 9-5
PORTG_FER (function enable) register,
9-10
PORTG_HYSTERESIS register,
port H
GPIO, 9-13
peripherals, 9-2
structure, 9-6
PORTH_FER (function enable) register,
9-10
PORTH_HYSTERESIS register,
port pins, 9-3, 18-39
port pins, test access, B-2
PORT_PREF0 bit, 2-5
PORT_PREF1 bit, 2-5
port width, PPI, 20-27
PORTx_FER (function enable) registers,
9-3, 9-12, 9-16, 9-30
PORTx_FER registers,
PORTxIO_BOTH (GPIO set on both
edges) registers, 9-34
PORTxIO_BOTH registers,
PORTxIO_CLEAR (GPIO clear) registers,
9-32
PORTxIO_CLEAR registers,
PORTxIO_DIR (GPIO direction)
registers, 9-30, 14-41, 14-42, 14-44,
14-47, 14-48, 14-49,
PORTxIO_DIR registers,
Index
9-24
9-25
9-25
9-30
9-34
9-32
14-50
9-30
I-29