Analog Devices ADSP-BF506F Hardware Reference Manual page 1307

UART
IrDA receiver pulse detection,
IrDA transmit pulse,
IrDA transmitter, 15-13
and ISRs, 15-23
loopback mode, 15-31
mixing modes, 15-25
non-DMA interrupt operation,
non-DMA mode, 15-22
receive operation, 15-8
receive sampling window,
registers, table, 15-27
signals, 15-4
standard, 15-1
string transmission, 15-51
switching from DMA to non-DMA,
15-25
switching from non-DMA to DMA,
15-26
and system DMA, 15-39
transmission, 15-7
transmission SYNC bit use,
UART divisor latch high byte
(UARTx_DLH) registers,
UART divisor latch low byte
(UARTx_DLL) registers,
UART global control (UARTx_GCTL)
registers, 15-45
UART interrupt enable clear
(UARTx_IER_CLEAR) registers,
15-39
UART interrupt enable registers
(UARTx_IER), 15-41
UART interrupt enable set
(UARTx_IER_SET) registers,
UART interrupt enable (UARTx_IER)
registers, 15-39
UART line control registers
(UARTx_LCR), 15-28
ADSP-BF50x Blackfin Processor Hardware Reference
(continued)
15-15
15-13
15-52
15-14
15-53
15-43
15-43
15-39
UART line control (UARTx_LCR)
registers, 15-28
UART line status registers (UARTx_LSR),
15-33
UART line status (UARTx_LSR) registers,
15-34
UART modem control (UARTx_MCR)
registers, 15-31
UART modem status (UARTx_MSR)
registers, 15-36
UART ports
overview, 1-19
UART receive buffer registers
(UARTx_RBR), 15-8
UART receive buffer (UARTx_RBR)
registers, 15-38
UART scratch registers (UARTx_SCR),
15-44
UART scratch (UARTx_SCR) registers,
15-44
UART transmit holding (UARTx_THR)
registers, 15-37
UARTx_DLH (UART divisor latch high
byte registers), 15-27
UARTx_DLH (UART divisor latch high
byte) registers, 15-43
UARTx_DLL, 15-27
UARTx_DLL (UART divisor latch low
byte registers), 15-27
UARTx_DLL (UART divisor latch low
byte) registers, 15-43
UARTx_GCTL (UART global control
registers), 15-27
UARTx_GCTL (UART global control)
registers, 15-45
UARTx_IER_CLEAR (UART interrupt
enable clear) registers,
UARTx_IER_SET (UART interrupt
enable set) registers,
Index
15-39
15-39
I-43