Analog Devices ADSP-BF506F Hardware Reference Manual page 1282

Index
frame sync
multichannel mode,
sampling edge, 19-33
SPORT options, 19-31
frame sync divider[15:0] field, 19-64,
19-65
frame synchronization
PPI in GP modes, 20-19
and SPORT, 19-3
frame sync polarity, PPI and timer,
frame sync pulse
use of, 19-51
when issued, 19-51
frame sync signal, control of, 19-50,
frame track error, 20-30,
frequencies, clock and frame sync,
frequency, DEB, 3-10
frequency, EAB, 3-10
FSDR (frame sync to data relationship) bit,
19-22, 19-66
F signal, 20-30
FT_ERR (frame track error) bit, 20-30,
20-33
full duplex, 19-4, 19-6
SPI, 18-2
FULL_ON bit, 8-21
full-on mode, 1-24, 8-8
function enable (PORTF_FER) register,
9-10
function enable (PORTG_FER) register,
9-10
function enable (PORTH_FER) register,
9-10
function enable (PORTx_FER) registers,
9-30
G
GCALL (general call) bit, 16-29,
general call address, TWI,
general-purpose interrupts, 4-2,
I-18
(continued)
19-19
20-20
19-55
20-33
19-26
16-30
16-10
4-3
ADSP-BF50x Blackfin Processor Hardware Reference
general-purpose I/O
overview, 1-9
general-purpose I/O. See GPIO
general-purpose ports,
assigning interrupt channels,
interrupt channels, 9-18
interrupt generation flow,
latency, 9-12
pin defaults, 9-3
pins, interrupt, 9-16
throughput, 9-12
general-purpose ports. See GPIO
general-purpose timers,
aborting immediately,
and startup errors, 10-8
autobaud mode, 10-32
block diagram, 10-59
buffer registers, 10-44
capture mode, 10-5
clock source, 10-3
code examples, 10-49
control bit summary,
counter, 10-4
disable timing, 10-23
enabling, 10-5, 10-34
error detection, 10-7
EXT_CLK mode, 10-44
external interface, 10-3
features, 10-2
flow diagram for EXT_CLK mode,
10-34
generating maximum frequency,
illegal states, 10-7, 10-9
internal interface, 10-4
internal timer structure,
interrupts, 10-4, 10-5, 10-15,
interrupt setup, 10-51
interrupt structure, 10-6
measurement report, 10-25, 10-27,
10-28
9-1 to 9-42
9-18
9-17
10-1 to 10-58
10-23
10-46
10-16
10-3
10-29