ST STM32L4+ Series Reference Manual page 1515

RM0432
42.4.16 Repetition Counter
The LPTIM features a repetition counter that decrements by 1 each time an LPTIM counter
overflow event occurs. A repetition counter underflow event is generated when the repetition
counter contains zero and the LPTIM counter overflows. Next to each repetition counter
underflow event, the repetition counter gets loaded with the content of the REP[7:0] bit-field
which belongs to the repetition register LPTIM_RCR.
A repetition underflow event is generated on each and every LPTIM counter overflow when
the REP[7:0] register is set to 0.
When PRELOAD = 1, writing to the REP[7:0] bit-field has no effect on the content of the
repetition counter until the next repetition underflow event occurs. The repetition counter
continues to decrement each LPTIM counter overflow event and only when a repetition
underflow event is generated, the new value written into REP[7:0] is loaded into the
repetition counter. This behavior is depicted in
Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only
Figure 450. Encoder mode counting sequence
T1
T2
Counter
up down
Figure 451.
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