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Low-power timer (LPTIM) applied to STM32L4P5xx and STM32L4Q5xx only
Interrupt event
Update Event
Repetition register
update Ok
42.7
LPTIM registers
42.7.1
LPTIM interrupt and status register (LPTIM_ISR)
Address offset: 0x000
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 REPOK: Repetition register update Ok
REPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_RCR
register has been successfully completed. REPOK flag can be cleared by writing 1 to the REPOKCF
bit in the LPTIM_ICR register.
Bit 7 UE: LPTIM update event occurred
UE is set by hardware to inform application that an update event was generated. UE flag can be
cleared by writing 1 to the UECF bit in the LPTIM_ICR register.
Bit 6 DOWN: Counter direction change up to down
In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has
changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the
LPTIM_ICR register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 42.3: LPTIM
Bit 5 UP: Counter direction change down to up
In Encoder mode, UP bit is set by hardware to inform application that the counter direction has
changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR
register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 42.3: LPTIM
Bit 4 ARROK: Autoreload register update OK
ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR
register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF
bit in the LPTIM_ICR register.
1518/2301
Table 308. Interrupt events (continued)
Interrupt flag is raised when the repetition counter underflows (or contains
zero) and the LPTIM counter overflows.
REPOK is set by hardware to inform application that the APB bus write
operation to the LPTIM_RCR register has been successfully completed.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
implementation.
implementation.
Description
24
23
22
Res.
Res.
Res.
8
7
6
REP
UE
DOWN
OK
r
r
r
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
ARR
CMP
EXT
UP
OK
OK
TRIG
r
r
r
r
RM0432
17
16
Res.
Res.
1
0
ARRM
CMPM
r
r
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