Fsi Command Register (Fsicmdr); Fsi Lpc Command Status Register 1 (Fsilstr1) - Renesas H8S/2100 Series Hardware Manual

Section 21 FSI Interface

21.3.13 FSI Command Register (FSICMDR)

FSICMDR stores command data during FSI command reception. FSICMDR stores command data
when the FSICMDI bit in FSILSTR1 is cleared to 0. It does not store command data when the
FSICMDI bit is set to 1.
Bit Bit Name
7 to 0 bit 7 to bit 0 All 0

21.3.14 FSI LPC Command Status Register 1 (FSILSTR1)

FSILSTR1 indicates the LPC internal status.
Bit Bit Name
7 CMDBUSY 0
6 FSICMDI
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REJ09B0452-0100
R/W
Initial
Value EC Host Description

R
R/W
Initial
Value EC Host Description
R/W* R
0 R/W* R
These bits store an FSI command.
FSI Command Busy Flag
0: The FSI command execution is completed.
[Clearing condition]
•
When this bit is read as 1 and then written with 0.
1: The FSI command execution is in progress.
[Setting condition]
•
When an FSI command is received.
FSI Command Interrupt Flag
0:The FSI command interrupt processing is
completed.
[Clearing condition]
•
When this bit is read as 1 and then written with 0.
1: The FSI command interrupt processing is in
progress.
[Setting condition]
•
When an FSI command is received.