Input/Output Diagrams - Texas Instruments MSPM0G350 Series Manual

MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023

8.31 Input/Output Diagrams

The IOMUX manages the selection of which peripheral function is to be used on a digital IO. It also provides the
controls for the output driver, input path, and the wake-up logic for wakeup from SHUTDOWN mode. For more
information, refer to the IOMUX section of the
Manual.
The mixed-signal IO pin slice diagram for a full featured IO pin is shown in
analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the
device-specific data sheet for detailed information on what features are supported for a specific pin.
WAKESTATE
WUEN D Q
EN
WCOMP D Q
EN
HYSTEN
INV
INENA
Unassigned
0
Peripheral 01 1
DIN
15
Peripheral 15
PF
INV
Unassigned
0
Peripheral 01 1
15
Peripheral 15
Unassigned
0
Peripheral 01 1
15
Peripheral 15
PC
PF != 0
Z1
DRV
PIPU
PIPD
SHUTDOWN
RELEASE
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MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Wake to PMCU
SHUTDOWN Wakeup
PC
S Q
R
Glitch
Filter
Input Logic
1
0
Output Logic
D Q
DOUT
1
EN
0
RSTN
D Q
Hi-Z
EN
RSTN
S
R Q
Figure 8-2. Superset Input/Output Diagram
Product Folder Links: MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
Figure
To analog peripheral function(s)
5V tolerant open drain IO (ODIO)
does not have PMOS control and
pull-up resistor
VDDIO
SHUTDOWN
Latches
D Q
EN
VSS
Driver
Logic
D Q
EN
D Q
EN
D Q
EN
D Q
EN
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8-2. Not all pins will have
VDDIO
PMOS
NMOS
VSS
IO pin