Dmac Bus Cycles (Dual Address Mode) - Renesas H8S/2633 Series Hardware Manual

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DMAC Bus Cycles (Dual Address Mode)

Short Address Mode: Figure 8-19 shows a transfer example in which TEND output is enabled

and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external

8-bit, 2-state access space to internal I/O space.

Figure 8-19 Example of Short Address Mode Transfer

A one-byte or one-word transfer is performed for one transfer request, and after the transfer the

bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC.

In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead

cycle is inserted after the DMA write cycle.

In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in

which the transfer counter reaches 0.

Last transfer