Timing Diagrams; Performance Graph - Analog Devices AD73360L Manual

AD73360L
t
2
Figure 1. MCLK Timing
TO OUTPUT
PIN
C
L
15pF
Figure 2. Load Circuit for Timing Specifications
t
1
MCLK
t
13
t
SCLK*
5
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
Figure 3. SCLK Timing
SE (I)
THREE-
STATE
SCLK (O)
SDIFS (I)
SDI (I)
t
THREE-
STATE
SDOFS (O)
THREE-
STATE
SDO (O)
t
1
t
3
100 A
I
OL
2.1V
100 A I
OH
t
t
2
3
t
6
t
4
t
7
t
8
D15
t
9
10
t
t
11
12
D15
Figure 4. Serial Port (SPORT)
80
70
60
50
40
30
20
10
0
–10
–85 –75 –65
Figure 5. S/(N+D) vs. V
Bandwidth (300 Hz–3.4 kHz)
t
D14 D1
D2 D1 D0
–4–
–55 –45 –35 –25 –15 –5
V – dBm0
IN
(ADC @ 3 V) Over Voiceband
IN
t
8
7
D0
D15
5
3.17
D15
D14
REV. 0