Spi Slave Mode Boot From Spi Host (Bmode = 100) - Analog Devices Blackfin ADSP-BF537 Hardware Reference Manual

Specific Blackfin Boot Modes
Once this information is processed, the on-chip boot ROM again issues a
read command and sends out address 0x0018 to boot in block 1 of the
INIT code DXE.
SPICLK all
PF10 all
MOSI all
0
MISO all
DSP SENDS OUT
READ COMMAND*
*PROCESSOR SENDS OUT READ COMMAND (0x03) AND THEN TWO
ADDRESS BYTES (ADDR[15:8] EQUALS 0x0, ADDR[7:0] EQUALS 0x18).
Figure 19-21. SPI Master Mode Boot Sequence: Boot Block 1 of INIT
Code DXE

SPI Slave Mode Boot From SPI Host (BMODE = 100)

For SPI slave mode boot (
ured as an SPI slave device and a host is used to boot the processor. The
hardware configuration shown in
The host drives the SPI clock and is therefore responsible for the timing.
The host must provide an active-low chip select signal that connects to the
input of the Blackfin processor on pin
SPISS
byte transferred or remain low during the entire procedure. In SPI slave
boot mode, the boot kernel sets the
register. Therefore, the
SPI_CTL
the pin. See
MOSI
Eight-bit data is expected; 16-bit mode is not supported.
19-48
0 0 0 0
1 0
0x66 0x01 0x67
=
BMODE
Figure 19-22
MISO
"SPI Transfer Protocols" on page 10-14
ADSP-BF537 Blackfin Processor Hardware Reference
0
0 0 0 0
0 1 0
0x01 0x40 0x05 0xC0
BLOCK 1 OF INIT CODE DXE. . .
), the Blackfin processor is config-
100
is assumed.
. It can toggle with each
PF14
bit and clears the
CPHA
pin is latched on the falling edge of
0
0 0 0 0
0 1
0x04 0x08 0xE1
bit in the
CPOL
for details.