Enhanced Emulation Status Register - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Table A-71. BRKCTL Register Bit Descriptions (Cont'd)
Bit Name
25 UMODE
26 ENBIOY
27 ENBIOX
31–28 Reserved

Enhanced Emulation Status Register

The
EEMUSTAT
run on the ADSP-21367/8/9 and ADSP-2137x processors. This register is
a memory-mapped IOP register that can be accessed by the core. The
register contains two status bits that report I/O breakpoints, one
EEMUSTAT
each for the two I/O buses (IOX and IOY).
When a breakpoint is reached, an interrupt occurs and the breakpoint's
status bits are set. When the core returns from an interrupt, the break-
point's status bits are cleared. This register is shown in
described in Table
ADSP-21368 SHARC Processor Hardware Reference
Description
User Mode Breakpoint Functionality Enable. Address Break-
point 3.
0 = Disable user controlled breakpoint
1 = Enable user controlled breakpoint
IOY Breakpoint Enable.
0 = Disable IOY breakpoint
1 = Enable IOY breakpoint 0
IOX Breakpoint Enable.
0 = Disable IOX breakpoint
1 = Enable IOX breakpoint
register reports the breakpoint status of the programs that
A-72.
Register Reference
Figure A-86 and
A-179