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ST STM32F301 6 Series Reference Manual

Advanced arm-based 32-bit mcus

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RM0366

Reference manual

STM32F301x6/8 and STM32F318x8

®

advanced Arm

-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F301x6/8 and STM32F318x8 microcontroller memory and

peripherals. The STM32F301x6/8 and STM32F318x8 devices will be referred to as

"STM32F3xx" throughout the document, unless otherwise specified.

The STM32F3xx is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

applicable datasheets.

®

®

®

For information on the Arm

Cortex

-M4 core with FPU, refer to the Cortex

-M4F technical

reference manual.

STM32F3xx microcontrollers include ST state-of-the-art patented technology.

Related documents

Available from STMicroelectronics web site www.st.com:

• STM32F301x6/8 and STM32F318x8 datasheets

• STM32F301x6/8 device errata sheet (ES0237)

• STM32F318 device errata sheet (ES0257)

®

• STM32F3xx/STM32F4xx Cortex

-M4 programming manual (PM0214)

February 2025

RM0366 Rev 5

1/874

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Summary of Contents for ST STM32F301 6 Series

Page 1 For information on the Arm Cortex -M4 core with FPU, refer to the Cortex -M4F technical reference manual. STM32F3xx microcontrollers include ST state-of-the-art patented technology. Related documents Available from STMicroelectronics web site www.st.com: • STM32F301x6/8 and STM32F318x8 datasheets • STM32F301x6/8 device errata sheet (ES0237) •...
Page 2 Contents RM0366 Contents Documentation conventions ....... . . 36 General information ......... 36 List of abbreviations for registers .
Page 3 RM0366 Contents Flash register description ........58 3.5.1 Flash access control register (FLASH_ACR) .
Page 4 Contents RM0366 6.2.3 External NPOR signal ........80 Low-power modes .
Page 5 RM0366 Contents 7.4.2 Clock configuration register (RCC_CFGR) ..... 104 7.4.3 Clock interrupt register (RCC_CIR) ......106 7.4.4 APB2 peripheral reset register (RCC_APB2RSTR) .
Page 6 Contents RM0366 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to D and F) ......... 137 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to D and F) .
Page 7 RM0366 Contents 10.4.1 DMA block diagram ........156 10.4.2 DMA transfers .
Page 8 Contents RM0366 11.3.9 Rising trigger selection register (EXTI_RTSR2) ....189 11.3.10 Falling trigger selection register (EXTI_FTSR2) ....190 11.3.11 Software interrupt event register (EXTI_SWIER2) .
Page 9 RM0366 Contents 12.3.26 Data management ........226 12.3.27 Dynamic low-power features .
Page 10 Contents RM0366 13.1 Introduction ..........278 13.2 DAC1 main features .
Page 11 RM0366 Contents 14.5.1 COMP2 control and status register (COMP2_CSR) ....296 14.5.2 COMP4 control and status register (COMP4_CSR) ....298 14.5.3 COMP6 control and status register (COMP6_CSR) .
Page 12 Contents RM0366 16.6.1 TSC control register (TSC_CR) ......321 16.6.2 TSC interrupt enable register (TSC_IER) ..... . 324 16.6.3 TSC interrupt clear register (TSC_ICR) .
Page 13 RM0366 Contents 17.3.21 Encoder interface mode ........379 17.3.22 UIF bit remapping .
Page 14 Contents RM0366 17.4.21 TIM1 DMA control register (TIM1_DCR) ..........418 17.4.22 TIM1 DMA address for full transfer (TIM1_DMAR) .
Page 15 RM0366 Contents 18.4 TIM2 registers ..........472 18.4.1 TIM2 control register 1 (TIM2_CR1) .
Page 16 Contents RM0366 19.4.8 Forced output mode ........513 19.4.9 Output compare mode .
Page 17 RM0366 Contents 19.5.19 TIM15 register map ........553 19.6 TIM16/TIM17 registers .
Page 18 Contents RM0366 20.4.5 TIM6 event generation register (TIM6_EGR) ....585 20.4.6 TIM6 counter (TIM6_CNT) ........585 20.4.7 TIM6 prescaler (TIM6_PSC) .
Page 19 RM0366 Contents 23.4.3 IWDG reload register (IWDG_RLR) ......600 23.4.4 IWDG status register (IWDG_SR) ......601 23.4.5 IWDG window register (IWDG_WINR) .
Page 20 Contents RM0366 24.6.9 RTC write protection register (RTC_WPR) ..... 634 24.6.10 RTC sub second register (RTC_SSR) ......634 24.6.11 RTC shift control register (RTC_SHIFTR) .
Page 21 RM0366 Contents 25.6 I2C interrupts ..........696 25.7 I2C DMA requests .
Page 22 Contents RM0366 26.5.11 USART synchronous mode ....... . . 738 26.5.12 USART single-wire half-duplex communication .
Page 23 RM0366 Contents 27.5.7 Configuration of SPI ........790 27.5.8 Procedure for enabling SPI .
Page 24 Contents RM0366 28.3 SWJ debug port (serial wire and JTAG) ......838 28.3.1 Mechanism to select the JTAG-DP or the SW-DP ....839 28.4 Pinout and debug port pins .
Page 25 RM0366 Contents 28.15.6 TRACE pin assignment ........858 28.15.7 TPUI formatter .
Page 26 List of tables RM0366 List of tables Table 1. STM32F3xx peripheral register boundary addresses ......42 Table 2.
Page 27 RM0366 List of tables Table 47. DAC register map and reset values ......... 291 Table 48.
Page 28 List of tables RM0366 Table 97. I2C interrupt requests ........... . 696 Table 98.
Page 29 RM0366 List of figures List of figures Figure 1. System architecture ........... . . 38 Figure 2.
Page 30 List of figures RM0366 Figure 45. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) ....221 Figure 46. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)....221 Figure 47.
Page 31 RM0366 List of figures Figure 93. Counter timing diagram with prescaler division change from 1 to 2 ....336 Figure 94. Counter timing diagram with prescaler division change from 1 to 4 ....336 Figure 95.
Page 32 List of figures RM0366 Figure 145. Control circuit in reset mode ..........385 Figure 146.
Page 33 RM0366 List of figures Figure 197. Triggering TIM2 with Enable of TIM1 ........469 Figure 198.
Page 34 List of figures RM0366 Figure 245. RTC block diagram ............606 Figure 246.
Page 35 RM0366 List of figures Figure 294. IrDA data modulation (3/16) - normal mode ........747 Figure 295.
Page 36 Documentation conventions RM0366 Documentation conventions General information ®(a) ® The STM32F3xx devices have an Arm Cortex -M4F core. List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit.
Page 37 RM0366 Documentation conventions Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is unmodified are marked as U. Glossary This section gives a brief definition of acronyms and abbreviations used in this document: • Word: data of 32-bit length. •...
Page 38 System and memory overview RM0366 System and memory overview System architecture The STM32F318x8 main system consists of: • Four masters: ® – Cortex -M4 core I-bus ® – Cortex -M4 core D-bus ® – Cortex -M4 core S-bus – DMA1 (general-purpose DMA) •...
Page 39 RM0366 System and memory overview 2.1.1 S0: I-bus ® This bus connects the instruction bus of the Cortex -M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory and the SRAM up to 16 Kbytes.
Page 40 RM0366 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 41 RM0366 2.2.2 Memory map and register boundary addresses All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table. The following table gives the boundary addresses of the peripherals available in the devices.
Page 42 RM0366 Table 1. STM32F3xx peripheral register boundary addresses Size Boundary address Peripheral Peripheral register map (bytes) AHB3 0x5000 0000 - 0x5000 03FF ADC1 Section 12.7 on page 274 0x4800 1800 - 0x4FFF FFFF ~132 M Reserved 0x4800 1400 - 0x4800 17FF GPIOF Section 8.4.12 on page 142 0x4800 1000 - 0x4800 13FF...
Page 43 RM0366 Table 1. STM32F3xx peripheral register boundary addresses (continued) Size Boundary address Peripheral Peripheral register map (bytes) 0x4000 7C00 - 0x4000 9BFF Reserved 0x4000 7800 - 0x4000 7BFF I2C3 Section 25.9.12 on page 711 0x4000 7400 - 0x4000 77FF DAC1 Section 13.9.8 on page 291 0x4000 7000 - 0x4000 73FF Section 6.4.3 on page 89...
Page 44 RM0366 Embedded SRAM STM32F3xx devices feature up to 16 Kbytes of static SRAM. It can be accessed as bytes, halfwords (16 bits) or full words (32 bits). Up to 16 Kbytes of SRAM can be addressed at maximum system clock frequency without wait state, and can be accessed by both CPU and DMA.
Page 45 (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000). 2.5.1 Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory through: •...
Page 46 Embedded flash memory RM0366 Embedded flash memory Flash main features Up to 64 Kbytes of flash memory • Memory organization: – Main memory block: 8 Kbits × 64 bitsInformation block: 1280 × 64 bits Flash memory interface (FLITF) features: • Read interface with prefetch buffer (2 ×...
Page 47 USART2, or on devices with internal regulator ON and USART, I2C or SPI on devices with internal regulator OFF. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, refer to the AN2606 available from www.st.com. • Option bytes 3.2.2...
Page 48 Embedded flash memory RM0366 Prefetch buffer The prefetch buffer is 2 blocks wide where each block consists of 8 bytes. The prefetch blocks are direct-mapped. A block can be completely replaced on a single read to the flash memory as the size of the block matches the bandwidth of the flash memory. The implementation of this prefetch buffer makes a faster CPU execution possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer.
Page 49 RM0366 Embedded flash memory 3.2.3 Flash program and erase operations The STM32F3xx embedded flash memory can be programmed using in-circuit programming or in-application programming. The in-circuit programming (ICP) method is used to update the entire contents of the flash memory, using the JTAG, SWD protocol or the bootloader to load the user application into the microcontroller.
Page 50 Embedded flash memory RM0366 Main flash memory programming The main flash memory can be programmed 16 bits at a time. The program operation is started when the CPU writes a half-word into a main flash memory address with the PG bit of the FLASH_CR register set.
Page 51 RM0366 Embedded flash memory The main flash memory programming sequence in standard mode is as follows: Check that no main flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. Set the PG bit in the FLASH_CR register. Perform the data write (half-word) at the desired address.
Page 52 Embedded flash memory RM0366 Figure 3. Flash memory Page Erase procedure Read FLASH_CR_LOCK Perform unlock sequency FLASH_CR_LOCK Write FLASH_CR_PER to 1 Write into FAR an address within the page to erase Write FLASH_CR_STRT to 1 FLASH_SR_BSY Check EOP flag in FLASH_SR, and then clear it by software.
Page 53 RM0366 Embedded flash memory Figure 4. Flash memory Mass Erase procedure Read FLASH_CR_LOCK Perform unlock sequency FLASH_CR_LOCK Write into FLASH_CR_MER to 1 Write FLASH_CR_STRT to 1 FLASH_SR_BSY Check EOP flag in FLASH_SR, and then clear it by software. Option byte programming The option bytes are programmed differently from normal user addresses.
Page 54 Embedded flash memory RM0366 The sequence is as follows: • Check that no flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. • Unlock the OPTWRE bit in the FLASH_CR register. • Set the OPTPG bit in the FLASH_CR register •...
Page 55 The flash memory is protected when the RDP option byte and its complement contain the pair of values shown in Table Table 4. Flash memory read protection status RDP byte value RDP complement value Read protection level Level 0 (ST production 0xAA 0x55 configuration) Any value (not necessarily Any value except complementary)
Page 56 Embedded flash memory RM0366 Level 2: No debug ® In this level, the protection level 1 is ensured. In addition, the Cortex -M4 debug capabilities are disabled. Consequently, the debug port, the boot from RAM (boot RAM mode) and the boot from the system memory (bootloader mode) are no more available.
Page 57 RM0366 Embedded flash memory 3.3.2 Write protection The write protection is implemented with a granularity of 2 pages. It is activated by configuring the WRP[1:0] option bytes, and then by reloading them by setting the OBL_LAUNCH bit in the FLASH_CR register. If a program or an erase operation is performed on a protected, the flash memory returns a WRPRTERR protection error flag in the Flash memory Status Register (FLASH_SR).
Page 58 Embedded flash memory RM0366 Flash register description The flash memory registers must be accessed by 32-bit words (half-word and byte accesses are not allowed). 3.5.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030 Res. Res. Res. Res.
Page 59 RM0366 Embedded flash memory Bits 31:0 FKEYR: Flash key These bits represent the keys to unlock the Flash. 3.5.3 Flash option key register (FLASH_OPTKEYR) Address offset: 0x08 Reset value: 0xXXXX XXXX All the register bits are write-only and return a 0 when read. OPTKEYR[31:16] OPTKEYR[15:0] Bits 31:0...
Page 60 Embedded flash memory RM0366 Bit 2 PGERR: Programming error Set by hardware when an address to be programmed contains a value different from '0xFFFF' before programming. Reset by writing 1. Note: The STRT bit in the FLASH_CR register should be reset before starting a programming operation.
Page 61 RM0366 Embedded flash memory Bit 7 LOCK: Lock Write to 1 only. When it is set, it indicates that the Flash is locked. This bit is reset by hardware after detecting the unlock sequence. In the event of unsuccessful unlock operation, this bit remains set until the next reset.
Page 62 Bit 8: WDG_SW Bits 7:3 Reserved, must be kept at reset value. Bits 2:1 RDPRT[1:0]: Read protection Level status 00: Read protection Level 0 is enabled (ST production set up) 01: Read protection Level 1 is enabled 10: Reserved 11: Read protection Level 2 is enabled Note: These bits are read-only.
Page 63 RM0366 Embedded flash memory 3.5.8 Write protection register (FLASH_WRPR) Address offset: 0x20 Reset value: 0xFFFF FFFF WRP[31:16] WRP[15:0] Bits 31:0 WRP: Write protect This register contains the write-protection option bytes loaded by the OBL. These bits are read-only. Flash register map Table 7.
Page 64 Embedded flash memory RM0366 Table 7. Flash interface - register map and reset values (continued) Offset Register FLASH_ 0x01C Reset value FLASH_ WRP[31:0] WRPR 0x020 Reset value Refer to Section 2.2 on page 40 for the register boundary addresses. 64/874 RM0366 Rev 5...
Page 65 RM0366 Option byte description Option byte description There are six option bytes. They are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode. A 32-bit word is split up as follows in the option bytes. Table 8.
Page 66 Option byte description RM0366 Table 10. Description of the option bytes Flash memory Option bytes address Bits [31:24]: nUSER Bits [23:16]: USER: User option byte (stored in FLASH_OBR[15:8]) This byte is used to configure the following features: - Select the watchdog event: Hardware or software - Reset event when entering Stop mode - Reset event when entering Standby mode Bits 23:22: Reserved...
Page 67 RM0366 Option byte description Table 10. Description of the option bytes (continued) Flash memory Option bytes address Datax: Two bytes for user data storage. These addresses can be programmed using the option byte programming procedure. 0x1FFF F804 Bits [31:24]: nData1 Bits [23:16]: Data1 (stored in FLASH_OBR[31:24]) Bits [15:8]: nData0 Bits [7:0]: Data0 (stored in FLASH_OBR[23:16])
Page 68 Cyclic redundancy check calculation unit (CRC) RM0366 Cyclic redundancy check calculation unit (CRC) Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 69 RM0366 Cyclic redundancy check calculation unit (CRC) CRC functional description 5.3.1 CRC block diagram Figure 5. CRC calculation unit block diagram 32-bit AHB bus read access write access 32-bit accesses Data register Data register crc_hclk (output) (input) CRC_INIT CRC_CR CRC computation CRC_POL CRC_IDR MS19882V3...
Page 70 Cyclic redundancy check calculation unit (CRC) RM0366 The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write.
Page 71 RM0366 Cyclic redundancy check calculation unit (CRC) CRC registers The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned bytes. For the other registers only 32-bit accesses are allowed. 5.4.1 CRC data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF DR[31:16] DR[15:0] Bits 31:0 DR[31:0]: Data register bits...
Page 72 Cyclic redundancy check calculation unit (CRC) RM0366 5.4.3 CRC control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. REV_ Res. Res. Res. Res. Res.
Page 73 RM0366 Cyclic redundancy check calculation unit (CRC) 5.4.4 CRC initial value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF CRC_INIT[31:16] CRC_INIT[15:0] Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value This register is used to write the CRC initial value. 5.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C1 1DB7 POL[31:16]...
Page 74 Cyclic redundancy check calculation unit (CRC) RM0366 5.4.6 CRC register map Table 12. CRC register map and reset values Offset Register name CRC_DR DR[31:0] 0x00 Reset value CRC_IDR IDR[7:0] 0x04 Reset value CRC_CR 0x08 Reset value CRC_INIT CRC_INIT[31:0] 0x10 Reset value CRC_POL POL[31:0] 0x14...
Page 75 RM0366 Power control (PWR) Power control (PWR) Power supplies An internal regulator is embedded in the STM32F3xx devices. • The internal regulator is enabled in the STM32F3xx MCUs: The STM32F301x6/8 devices require a 2.0 V - 3.6 V operating supply voltage (V and a 2.0 V - 3.6 V analog supply voltage (V ).
Page 76 Power control (PWR) RM0366 Figure 7. Power supply overview (STM32F318xx devices) domain A/D converter D/A converter Temp. sensor Reset block 1.8 V domain domain DDIO I/O ring Core Memories Wakeup logic, IWDG Digital peripherals NPOR Backup domain LSE crystal 32K osc BKP registers RCC BDCR register MSv34220V1...
Page 77 RM0366 Power control (PWR) 6.1.1 Independent A/D and D/A converter supply and reference voltage To improve conversion accuracy, the ADC and the DAC have an independent power supply, which can be separately filtered and shielded from noise on the PCB. The ADC and DAC voltage supply input is available on a separate VDDA pin.
Page 78 Power control (PWR) RM0366 When the RTC domain is supplied by V (analog switch connected to V ), the following functions are available: • PC13, PC14, and PC15 can be used as GPIO pins • PC13, PC14, and PC15 can be configured by RTC or LSE (refer to Section 24.3: RTC functional description on page 606)
Page 79 RM0366 Power control (PWR) Figure 8. Power on reset/power down reset waveform V DD /V DDA 40 mV hysteresis Reset MS19669V1 6.2.2 Programmable voltage detector (PVD) User can use the PVD to monitor the V power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Power control register (PWR_CR).
Page 80 Power control (PWR) RM0366 Figure 9. PVD thresholds V DD 100 mV PVD threshold hysteresis PVD output MS19670V1 Note: In the STM32F318x8 devices (V = 1.8 V ± 8%), the POR, PDR, and PVD features are not available. The Power on reset signal is applied on the NPOR pin. See details in the following section.
Page 81 RM0366 Power control (PWR) In addition, the power consumption in Run mode can be reduce by one of the following means: • Slowing down the system clocks • Gating the clocks to the APB and AHB peripherals when they are unused. Table 13.
Page 82 Power control (PWR) RM0366 6.3.3 Sleep mode Entering Sleep mode The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions. Two options are available to select the Sleep mode entry mechanism, ® ®...
Page 83 RM0366 Power control (PWR) Table 15. Sleep-on-exit Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 1 Refer to the Cortex-M4 System Control register. Mode exit Interrupt: refer to Table 28: STM32F3xx vector table.
Page 84 Power control (PWR) RM0366 Refer to Table 16 for more details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wake-up event, the HSI RC oscillator is selected as the system clock. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode.
Page 85 RM0366 Power control (PWR) Entering Standby mode Refer to Table 17 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Page 86 Power control (PWR) RM0366 Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby ® ® mode while the debug features are used. This is because the Arm Cortex -M4 core is no longer clocked.
Page 87 RM0366 Power control (PWR) Power control registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by wake-up from Standby mode) Res. Res. Res. Res.
Page 88 Power control (PWR) RM0366 Bit 2 CWUF: Clear wakeup flag. This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write) Bit 1 PDDS: Power down deepsleep. This bit is set and cleared by software. It works together with the LPDS bit. 0: Enter Stop mode when the CPU enters Deepsleep.
Page 89 RM0366 Power control (PWR) Bit 3 VREFINTRDYF: V Ready. Read Only. This bit indicates the state of the REFINT internal reference voltage. It is set when V is ready. It is reset during REFINT stabilization of V REFINT Note: This flag is useful only for the product bypassing the internal regulator and using external NPOR Pin, the internal POR waits the V stabilization REFINT...
Page 90 Reset and clock control (RCC) RM0366 Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 7.1.1 Power reset A power reset is generated when one of the following events occurs: Power-on/power-down reset (POR/PDR reset) When exiting Standby mode A power reset sets all registers to their reset values except the RTC domain (see...
Page 91 RM0366 Reset and clock control (RCC) Figure 10. Simplified diagram of the reset circuit External System reset Filter reset NRST WWDG reset IWDG reset Pulse Power reset generator Software reset (min 20 μs) Low-power management reset Option byte loader reset Exit from Standby mode MS19841V4 Software reset...
Page 92 Reset and clock control (RCC) RM0366 The backup registers are also reset when one of the following events occurs: RTC tamper detection event. Change of the read out protection from level 1 to level 0. Clocks Three different clock sources can be used to drive the system clock (SYSCLK): •...
Page 93 RM0366 Reset and clock control (RCC) Figure 11. STM32F3xx clock tree FLITFCLK to Flash programming interface to I2Cx (x = 1,2,3) SYSCLK I2SSRC SYSCLK to I2Sx (x = 2,3) Ext. clock I2S_CKIN 8 MHz HSI RC HCLK to AHB bus, core, memory and DMA to cortex System timer PLLSRC...
Page 94 Reset and clock control (RCC) RM0366 ® FCLK acts as Cortex -M4F free-running clock. For more details, refer to the STM32 ® Cortex -M4 MCUs and MPUs programming manual (PM0214). 7.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: •...
Page 95 Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 96 Reset and clock control (RCC) RM0366 The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware. The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR).
Page 97 RM0366 Reset and clock control (RCC) External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. Select this mode by setting the LSEBYP and LSEON bits in the RTC domain control register (RCC_BDCR).
Page 98 Reset and clock control (RCC) RM0366 causes a switch of the system clock to the HSI oscillator and the disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too.
Page 99 RM0366 Reset and clock control (RCC) 7.2.11 Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. 7.2.12 I2S clock The I2S clock can be either the System clock or an external clock provided on I2S_CKIN...
Page 100 Reset and clock control (RCC) RM0366 The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP [1:0] bits in the TIM16_OR register. The possibilities available are the following ones. •...
Page 101 RM0366 Reset and clock control (RCC) All U(S)ARTs and I2Cs have the capability to enable the HSI oscillator even when the MCU is in Stop mode (if HSI is selected as the clock source for that peripheral). All U(S)ARTs can also be driven by the LSE oscillator when the system is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE oscillator is enabled (LSEON) but they do not have the capability to turn on the LSE oscillator.
Page 102 Reset and clock control (RCC) RM0366 RCC registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. 7.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 (where X is undefined) Access: no wait state, word, half-word, and byte access Res.
Page 103 RM0366 Reset and clock control (RCC) Bit 17 HSERDY: HSE clock ready flag Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset. 0: HSE oscillator not ready 1: HSE oscillator ready Bit 16 HSEON: HSE clock enable...
Page 104 Reset and clock control (RCC) RM0366 7.4.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 wait state 2, word, half-word and byte access ≤ ≤ 1 or 2 wait states inserted only if the access occurs during clock source switch. PLLNO MCOPRE[2:0] Res.
Page 105 RM0366 Reset and clock control (RCC) Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4...
Page 106 Reset and clock control (RCC) RM0366 Bits 7:4 HPRE[3:0]: HLCK prescaler Set and cleared by software to control the division factor of the AHB clock. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128...
Page 107 RM0366 Reset and clock control (RCC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bits 22:21 Reserved, must be kept at reset value.
Page 108 Reset and clock control (RCC) RM0366 Bit 9 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 8 LSIRDYIE: LSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSI oscillator stabilization.
Page 109 RM0366 Reset and clock control (RCC) 7.4.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access TIM17 TIM16 TIM15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 110 Reset and clock control (RCC) RM0366 7.4.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word, and byte access I2C1 USART3 USART2 I2C3 DAC1 I2C2 Res. Res. Res. Res. Res. Res. Res.
Page 111 RM0366 Reset and clock control (RCC) Bit 16 Reserved, must be kept at reset value. Bit 15 SPI3RST: SPI3 reset Set and cleared by software. 0: No effect 1: Reset SPI3 and I2S3 Bit 14 SPI2RST: SPI2 reset Set and cleared by software. 0: No effect 1: Reset SPI2 and I2S2 Bits 13:12 Reserved, must be kept at reset value.
Page 112 Reset and clock control (RCC) RM0366 Bits 31:30 Reserved, must be kept at reset value. Bit 28 ADC1EN: ADC1 Set and reset by software. 0: ADC1 clock disabled 1: ADC1 clock enabled Bits 27:25 Reserved, must be kept at reset value. Bit 24 TSCEN: Touch sensing controller clock enable Set and cleared by software.
Page 113 RM0366 Reset and clock control (RCC) Bit 2 SRAMEN: SRAM interface clock enable Set and cleared by software to disable/enable SRAM interface clock during Sleep mode. 0: SRAM interface clock disabled during Sleep mode. 1: SRAM interface clock enabled during Sleep mode Bit 1 Reserved, must be kept at reset value.
Page 114 Reset and clock control (RCC) RM0366 Bit 14 USART1EN: USART1 clock enable Set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 TIM1EN: TIM1 timer clock enable Set and cleared by software.
Page 115 RM0366 Reset and clock control (RCC) Bit 28 PWREN: Power interface clock enable Set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enabled Bits 27:23 Reserved, must be kept at reset value. Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software.
Page 116 Reset and clock control (RCC) RM0366 Bit 4 TIM6EN: TIM6 timer clock enable Set and cleared by software. 0: TIM6 clock disabled 1: TIM6 clock enabled Bits 3:1 Reserved, must be kept at reset value. Bit 0 TIM2EN: TIM2 timer clock enable Set and cleared by software.
Page 117 RM0366 Reset and clock control (RCC) 7.4.9 RTC domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0018 (reset by RTC domain Reset) Access: 0 wait state 3, word, half-word, and byte access ≤ ≤ Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL, and RTCEN bits of the RTC domain control register...
Page 118 Reset and clock control (RCC) RM0366 Bit 2 LSEBYP: LSE oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: LSE oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable.
Page 119 RM0366 Reset and clock control (RCC) Bit 28 SFTRSTF: Software reset flag Set by hardware when a software reset occurs. Cleared by writing to the RMVF bit. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR flag Set by hardware when a POR/PDR occurs.
Page 120 Reset and clock control (RCC) RM0366 7.4.11 AHB peripheral reset register (RCC_AHBRSTR) Address: 0x28 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access ADC1R Res. Res. Res. Res. Res. Res. Res. F RST Res. D RST C RST B RST A RST...
Page 121 RM0366 Reset and clock control (RCC) Bit 18 GPIOBRST: I/O port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 17 GPIOARST: I/O port A reset Set and cleared by software. 0: No effect 1: Reset I/O port A Bits 16:0 Reserved, must be kept at reset value.
Page 122 Reset and clock control (RCC) RM0366 Bits 3:0 PREDIV: PREDIV division factor These bits are set and cleared by software to select PREDIV division factor. They can be written only when the PLL is disabled. Note: Bit 0 is the same bit as bit17 in Clock configuration register (RCC_CFGR), so modifying bit17...
Page 123 RM0366 Reset and clock control (RCC) Bit 11 TIM16SW: Timer16 clock source selection Set and reset by software to select TIM16 clock source. The bit is writable only when the following conditions occur: system clock source is the PLL and AHB or APB2 subsystem clocks are not divided by more than 2 cumulatively. The bit is reset by hardware when exiting from the previous condition (user must set the bit again in case of a new switch is required) 0: PCLK2 clock (doubled frequency when prescaled) (default)
Page 124 Reset and clock control (RCC) RM0366 7.4.14 RCC register map Table 19. RCC register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x00 Reset value PLLMUL PPRE2 PPRE1 RCC_CFGR HPRE[3:0] [2:0] [3:0] [2:0] [2:0] [1:0] [1:0] 0x04 Reset value RCC_CIR 0x08 Reset value...
Page 125 RM0366 Reset and clock control (RCC) Table 19. RCC register map and reset values (continued) Offset Register RCC_CSR 0x24 Reset value RCC_AHBRSTR 0x28 Reset value ADC1PRES RCC_CFGR2 PREDIV[3:0] [4:0] 0x2C Reset value RCC_CFGR3 0x30 Reset value Refer to Section 2.2 on page 40 for the register boundary addresses.
Page 126 General-purpose I/Os (GPIO) RM0366 General-purpose I/Os (GPIO) Introduction GPIO main features • Output states: push-pull or open drain + pull-up/down • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output) • Speed selection for each I/O • Input states: floating, pull-up/down, analog •...
Page 127 RM0366 General-purpose I/Os (GPIO) Figure 14. Basic structure of an I/O port bit Analog To on-chip peripheral Alternate function input on/off Read Protection trigger on/off diode Pull Input driver I/O pin Write Output driver on/off Protection Pull down diode P-MOS Output control N-MOS...
Page 128 General-purpose I/Os (GPIO) RM0366 Table 20. Port bit configuration table MODER(i) OSPEEDR(i) PUPDR(i) OTYPER(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 129 RM0366 General-purpose I/Os (GPIO) All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register. 8.3.2 I/O pin alternate function multiplexer and mapping The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time.
Page 130 General-purpose I/Os (GPIO) RM0366 8.3.3 I/O port control registers Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push- pull or open-drain) and speed.
Page 131 RM0366 General-purpose I/Os (GPIO) The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and F)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.
Page 132 General-purpose I/Os (GPIO) RM0366 Figure 16. Input floating / pull up / pull down configurations Read V DD V DD on/off TTL Schmitt protection trigger diode pull Write input driver I/O pin on/off output driver protection pull diode down V SS V SS Read/write ai15940b...
Page 133 RM0366 General-purpose I/Os (GPIO) Figure 17 shows the output configuration of the I/O port bit. Figure 17. Output configuration Read TTL Schmitt trigger on/off protection Write Input driver diode pull I/O pin Output driver on/off P-MOS protection pull down diode Output control Read/write...
Page 134 General-purpose I/Os (GPIO) RM0366 Figure 18 shows the alternate function configuration of the I/O port bit. Figure 18. Alternate function configuration To on-chip Alternate function input peripheral Read TTL Schmitt on/off trigger protection diode Pull Input driver Write I/O pin on/off Output driver protection...
Page 135 RM0366 General-purpose I/Os (GPIO) 8.3.13 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.
Page 136 General-purpose I/Os (GPIO) RM0366 GPIO registers For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x = A to D and F) Address offset:0x00 Reset value: 0xA800 0000 for port A...
Page 137 RM0366 General-purpose I/Os (GPIO) 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to D and F) Address offset: 0x08 Reset value: 0xC000 0000 (for port A) Reset value: 0x0000 00C0 (for port B) Reset value: 0x0000 0000 (for other ports) OSPEEDR15 OSPEEDR14 OSPEEDR13...
Page 138 General-purpose I/Os (GPIO) RM0366 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A to D and F) Address offset: 0x10 Reset value: 0x0000 XXXX Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 139 RM0366 General-purpose I/Os (GPIO) 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to D and F) Address offset: 0x18 Reset value: 0x0000 0000 BR15 BR14 BR13 BR12 BR11 BR10 BS15 BS14 BS13 BS12 BS11 BS10 Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0) These bits are write-only.
Page 140 General-purpose I/Os (GPIO) RM0366 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 141 RM0366 General-purpose I/Os (GPIO) 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to D and F) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 142 General-purpose I/Os (GPIO) RM0366 8.4.12 GPIO register map The following table gives the GPIO register map and reset values. Table 21. GPIO register map and reset values Offset Register name GPIOA_MODER 0x00 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 GPIOB_MODER 0x00 Reset value...
Page 143 RM0366 General-purpose I/Os (GPIO) Table 21. GPIO register map and reset values (continued) Offset Register name GPIOB_PUPDR 0x0C Reset value 0 0 0 0 0 0 0 0 0 0 0 0 GPIOx_IDR (where x = A..D and 0x10 Reset value GPIOx_ODR (where x = A..D and 0x14...
Page 144 System configuration controller (SYSCFG) RM0366 System configuration controller (SYSCFG) The STM32F3xx devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Enabling/disabling I C Fm+ on some I/O ports • Remapping some DMA trigger sources from TIM16, TIM17, TIM6, DAC1_CH1 to different DMA channels •...
Page 145 RM0366 System configuration controller (SYSCFG) Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input normal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation interrupt enable Bit 25 Reserved, must be kept at reset value.
Page 146 System configuration controller (SYSCFG) RM0366 Bit 11 TIM16_DMA_RMP: TIM16 DMA request remapping bit This bit is set and cleared by software. It controls the remapping of TIM16 DMA request. 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3) 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) Bits 10:7 Reserved, must be kept at reset value.
Page 147 RM0366 System configuration controller (SYSCFG) Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI3[3:0]: EXTI 3 configuration bits These bits are written by software to select the source input for the EXTI3 external interrupt. x000: PA[3] pin x001: PB[3] pin x010: PC[3] pin other configurations: reserved...
Page 148 System configuration controller (SYSCFG) RM0366 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI7[3:0]: EXTI 7 configuration bits These bits are written by software to select the source input for the EXTI7 external interrupt. x000: PA[7] pin x001: PB[7] pin x010: PC[7] pin Other configurations: reserved...
Page 149 RM0366 System configuration controller (SYSCFG) Bits 15:12 EXTI11[3:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. x000: PA[11] pin x001: PB[11] pin x010: PC[11] pin other configurations: reserved Bits 11:8 EXTI10[3:0]: EXTI 10 configuration bits These bits are written by software to select the source input for the EXTI10 external interrupt.
Page 150 System configuration controller (SYSCFG) RM0366 Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 EXTI15[3:0]: EXTI15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt. x000: PA[15] pin x001: PB[15] pin x010: PC[15] pin Other configurations: reserved Bits 11:8 EXTI14[3:0]: EXTI14 configuration bits...
Page 151 RM0366 System configuration controller (SYSCFG) Bits 31:3 Reserved, must be kept at reset value Bit 3 Reserved, must be kept at reset value Bit 2 PVD_LOCK: PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.
Page 152 Direct memory access controller (DMA) RM0366 Direct memory access controller (DMA) 10.1 Introduction The direct memory access (DMA) controller is a bus master and system peripheral. The DMA is used to perform programmable data transfers between memory-mapped peripherals and/or memories, upon the control of an off-loaded CPU. The DMA controller features a single AHB master architecture.
Page 153 RM0366 Direct memory access controller (DMA) 10.3 DMA implementation 10.3.1 DMA1 DMA1 is implemented with the hardware configuration parameters shown in the table below. Table 23. DMA implementation Feature Number of channels 10.3.2 DMA request mapping DMA controller The hardware requests from the peripherals (TIMx (x=1, 2, 15..17), ADC1, SPI[2,3], I2Cx (x=1..3), DAC_Channel1 and USARTx (x=1..3)) are simply logically ORed before entering the DMA.
Page 154 Direct memory access controller (DMA) RM0366 Figure 20. DMA request mapping Peripheral request signals Fixed hardware priority High priority ADC1 HW request 1 Channel 1 TIM2_CH3 TIM17_CH1 SW trigger 1 TIM17_UP (MEM2MEM bit) I2C3_TX USART3_TX HW request 2 Channel 2 TIM1_CH1 TIM2_UP SW trigger...
Page 155 RM0366 Direct memory access controller (DMA) Table 24. DMA requests for each channel Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel6 Channel7 ADC1 SPI3_RX SPI3_TX SPI2_RX SPI2_TX USART3_ USART USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX I2C3_TX I2C3_RX I2C2_TX I2C2_RX I2C1_TX...
Page 156 Direct memory access controller (DMA) RM0366 10.4 DMA functional description 10.4.1 DMA block diagram The DMA block diagram is shown in the figure below. Figure 21. DMA block diagram ICode FLITF Flash DCode Cortex-M4 System DCode SRAM (40K) GPIOA, B, C, D, F ADC 1 Ch.1 Bridge 2...
Page 157 RM0366 Direct memory access controller (DMA) 10.4.2 DMA transfers The software configures the DMA controller at channel level, to perform a block transfer, composed of a sequence of AHB bus transfers. A DMA block transfer may be requested from a peripheral, or triggered by the software in case of memory-to-memory transfer.
Page 158 Direct memory access controller (DMA) RM0366 10.4.3 DMA arbitration The DMA arbiter manages the priority between the different channels. When an active channel x is granted by the arbiter (hardware requested or software triggered), a single DMA transfer is issued (such as an AHB ‘read followed by write’ transfer of a single data).
Page 159 RM0366 Direct memory access controller (DMA) Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value.
Page 160 Direct memory access controller (DMA) RM0366 The three following use cases may happen: • Suspend and resume a channel This corresponds to the two following actions: – An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas DMA_CCRx.EN = 1). –...
Page 161 RM0366 Direct memory access controller (DMA) Memory-to-memory mode The DMA channels may operate without being triggered by a request from a peripheral. This mode is called memory-to-memory mode, and is initiated by software. If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates transfers.
Page 162 Direct memory access controller (DMA) RM0366 10.4.5 DMA data width, alignment, and endianness When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data alignments as described in the table below. Table 25. Programmable data width and endian behavior (when PINC = MINC = 1) Source Destinat Destination...
Page 163 RM0366 Direct memory access controller (DMA) Addressing AHB peripherals not supporting byte/half-word write transfers When the DMA controller initiates an AHB byte or half-word write transfer, the data are duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]). When the AHB slave peripheral does not support byte or half-word write transfers and does not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two examples below:...
Page 164 Direct memory access controller (DMA) RM0366 10.5 DMA interrupts An interrupt can be generated on a half transfer, transfer complete, or transfer error for each DMA channel x. Separate interrupt enable bits are available for flexibility. Table 26. DMA interrupt requests Interrupt Interrupt request Interrupt event...
Page 165 RM0366 Direct memory access controller (DMA) Bit 23 TEIF6: Transfer error (TE) flag for channel 6 0: No TE event 1: A TE event occurred. Bit 22 HTIF6: Half transfer (HT) flag for channel 6 0: No HT event 1:An HT event occurred. Bit 21 TCIF6: Transfer complete (TC) flag for channel 6 0: No TC event 1: A TC event occurred.
Page 166 Direct memory access controller (DMA) RM0366 Bit 8 GIF3: Global interrupt flag for channel 3 0: No TE, HT, or TC event 1: A TE, HT, or TC event occurred. Bit 7 TEIF2: Transfer error (TE) flag for channel 2 0: No TE event 1: A TE event occurred.
Page 167 RM0366 Direct memory access controller (DMA) Res. Res. Res. Res. CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, must be kept at reset value. Bit 27 CTEIF7: Transfer error flag clear for channel 7 Bit 26 CHTIF7: Half transfer flag clear for channel 7 Bit 25 CTCIF7: Transfer complete flag clear for channel 7...
Page 168 Direct memory access controller (DMA) RM0366 10.6.3 DMA channel x configuration register (DMA_CCRx) Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR are read-only when EN = 1.
Page 169 RM0366 Direct memory access controller (DMA) Bits 9:8 PSIZE[1:0]: Peripheral size Defines the data size of each DMA transfer to the identified peripheral. In memory-to-memory mode, this bitfield identifies the memory destination if DIR = 1 and the memory source if DIR = 0. In peripheral-to-peripheral mode, this bitfield identifies the peripheral destination if DIR = 1 and the peripheral source if DIR = 0.
Page 170 Direct memory access controller (DMA) RM0366 Bit 4 DIR: Data transfer direction This bit must be set only in memory-to-peripheral and peripheral-to-memory modes. 0: Read from peripheral – Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register. This is still valid in a memory-to-memory mode.
Page 171 RM0366 Direct memory access controller (DMA) Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data to transfer (0 to 2 - 1) This bitfield is updated by hardware when the channel is enabled: – It is decremented after each single DMA ‘read followed by write’...
Page 172 Direct memory access controller (DMA) RM0366 10.6.6 DMA channel x memory address register (DMA_CMARx) Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7) Reset value: 0x0000 0000 MA[31:16] MA[15:0] Bits 31:0 MA[31:0]: Peripheral address It contains the base address of the memory from/to which the data is read/written. When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored.
Page 173 RM0366 Direct memory access controller (DMA) Table 27. DMA register map and reset values (continued) Offset Register name DMA_CCR2 0x01C Reset value DMA_CNDTR2 NDTR[15:0] 0x020 Reset value DMA_CPAR2 PA[31:0] 0x024 Reset value DMA_CMAR2 MA[31:0] 0x028 Reset value 0x02C Reserved Reserved. DMA_CCR3 0x030 Reset value...
Page 174 Direct memory access controller (DMA) RM0366 Table 27. DMA register map and reset values (continued) Offset Register name DMA_CNDTR6 NDTR[15:0] 0x070 Reset value DMA_CPAR6 PA[31:0] 0x074 Reset value DMA_CMAR6 MA[31:0] 0x078 Reset value 0x07C Reserved Reserved. DMA_CCR7 0x080 Reset value DMA_CNDTR7 NDTR[15:0] 0x084...
Page 175 RM0366 Interrupts and events Interrupts and events 11.1 Nested vectored interrupt controller (NVIC) 11.1.1 NVIC main features • 66 maskable interrupt channels (not including the sixteen Cortex-M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) •...
Page 176 Interrupts and events RM0366 Table 28. STM32F3xx vector table (continued) Type of Acronym Description Address priority Settable SysTick System tick timer 0x0000 003C Settable WWDG Window Watchdog interrupt 0x0000 0040 Settable PVD through EXTI line 16 detection interrupt 0x0000 0044 Tamper and TimeStamp interrupts Settable TAMPER_STAMP...
Page 177 RM0366 Interrupts and events Table 28. STM32F3xx vector table (continued) Type of Acronym Description Address priority Reserved 0x0000 00B8 Settable I2C1_EV I2C1 event interrupt & EXTI Line23 interrupt 0x0000 00BC Settable I2C1_ER I2C1 error interrupt 0x0000 00C0 I2C2_EV I2C2 event interrupt 0x0000 00C4 I2C2_ER I2C2 error interrupt...
Page 178 Interrupts and events RM0366 Table 28. STM32F3xx vector table (continued) Type of Acronym Description Address priority Reserved 0x0000 013C COMP2 interrupt combined with EXTI Lines Settable COMP2 0x0000 0140 22 interrupt. COMP4 & COMP6 interrupts combined with Settable COMP4_6 0x0000 0144 EXTI Lines 30 and 32 interrupts respectively.
Page 179 RM0366 Interrupts and events generation, in addition, the internal lines are sampled only in STOP mode. This controller allows also to emulate the (only) external events by software, multiplexed with the corresponding hardware event line, by writing to a dedicated register. 11.2.1 Main features The EXTI main features are the following:...
Page 180 Interrupts and events RM0366 11.2.3 Wake-up event management STM32F3xx devices are able to handle external or internal events to wake up the core (WFE). The wake-up event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M4 System Control register.
Page 181 RM0366 Interrupts and events Hardware interrupt selection To configure a line as interrupt source, use the following procedure: • Configure the corresponding mask bit in the EXTI_IMR register. • Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR) •...
Page 182 Interrupts and events RM0366 11.2.6 External and internal interrupt/event line mapping 36 interrupt/event lines are available: 8 lines are internal (including the reserved ones); the remaining 28 lines are external. The GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 23.
Page 183 RM0366 Interrupts and events The remaining lines are connected as follows: • EXTI line 16 is connected to the PVD output • EXTI line 17 is connected to the RTC Alarm event • EXTI line 18 is reserved • EXTI line 19 is connected to RTC tamper and timestamps •...
Page 184 Interrupts and events RM0366 Bit 31 Reserved, must be kept at reset value. Bit 30 MRx: Interrupt Mask on external/internal line x (x = 30) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Bit 29 Reserved, must be kept at reset value.
Page 185 RM0366 Interrupts and events Bit 27 MRx: Event Mask on external/internal line x (x = 27) 0: Event request from Line x is masked 1: Event request from Line x is not masked Bit 27 Reserved, must be kept at reset value. Bit 26 Reserved, must be kept at reset value.
Page 186 Interrupts and events RM0366 Bits 20:19 TRx: Rising trigger event configuration bit of line x (x = 20 to 19) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Bit 18 Reserved, must be kept at reset value.
Page 187 RM0366 Interrupts and events Note: The external wake-up lines are edge-triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line.
Page 188 Interrupts and events RM0366 11.3.6 Pending register (EXTI_PR1) Address offset: 0x14 Reset value: 0x0000 0000 Res. PR30 Res. Res. Res. Res. Res. Res. Res. PR22 Res. PR20 PR19 Res. PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PR15 PR14 PR13 PR12 PR11 PR10...
Page 189 RM0366 Interrupts and events 11.3.7 Interrupt mask register (EXTI_IMR2) Address offset: 0x20 Reset value: 0xFFFF FFFE (See note below) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 190 Interrupts and events RM0366 Bits 31:1 Reserved, must be kept at reset value. Bit 0 TRx: Rising trigger event configuration bit of line x (x = 32) 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line. Note: The external wake-up lines are edge-triggered.
Page 191 RM0366 Interrupts and events Bits 31:1 Reserved, must be kept at reset value. Bit 0 SWIERx: Software interrupt on line x (x = 32) If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.
Page 192 Interrupts and events RM0366 Table 29. External interrupt/event controller register map and reset values (continued) Offset Register EXTI_FTSR1 TR[17:0] 0x0C Reset value EXTI_SWIER1 SWIER[17:0] 0x10 Reset value EXTI_PR1 PR[17:0] 0x14 Reset value EXTI_IMR2 0x20 Reset value EXTI_EMR2 0x24 Reset value EXTI_RTSR2 0x28 Reset value...
Page 193 RM0366 Analog-to-digital converters (ADC) Analog-to-digital converters (ADC) 12.1 Introduction 12.2 ADC main features • High-performance features – ADC1 is connected to 15 external channels + 3 internal channels – 12, 10, 8 or 6-bit configurable resolution – ADC conversion time: Fast channels: 0.19 µs for 12-bit resolution (5.1 Ms/s) Slow channels: 0.21 µs for 12-bit resolution (4.8 Ms/s) –...
Page 194 Analog-to-digital converters (ADC) RM0366 – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode • Interrupt generation at the end of conversion (regular or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or 3 or overrun events •...
Page 195 RM0366 Analog-to-digital converters (ADC) 12.3 ADC functional description 12.3.1 ADC block diagram Figure 24 shows the ADC block diagram and Table 31 gives the ADC pin description. Figure 24. ADC block diagram REF+ 1.8 to 3.6 V Cortex AREADY M4 with EOSMP ADC Interrupt JEOS...
Page 196 Analog-to-digital converters (ADC) RM0366 12.3.2 Pins and internal signals Table 30. ADC internal signals Signal Internal signal name Description type Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). EXT[15:0] Inputs These inputs are shared between the ADC master and the ADC slave.
Page 197 RM0366 Analog-to-digital converters (ADC) The input clock of the two ADCs (master and slave) can be selected between two different clock sources (see Figure 25: ADC clock scheme): The ADC clock can be a specific clock source, named “ADCxy_CK (xy=12 or 34) which is independent and asynchronous with the AHB clock”.
Page 198 Analog-to-digital converters (ADC) RM0366 Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio: •...
Page 199 RM0366 Analog-to-digital converters (ADC) 12.3.6 ADC voltage regulator (ADVREGEN) The sequence below is required to start ADC operations: Enable the ADC internal voltage regulator (refer to the ADC voltage regulator enable sequence). The software must wait for the startup time of the ADC voltage regulator ) before launching a calibration or enabling the ADC.
Page 200 Analog-to-digital converters (ADC) RM0366 12.3.8 Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) Each ADC provides an automatic calibration procedure which drives all the calibration sequence including the power-on/off sequence of the ADC. During the procedure, the ADC calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC until the next ADC power-off.
Page 201 RM0366 Analog-to-digital converters (ADC) Figure 27. ADC calibration ADCALDIF 0: Single-ended input 1: Differential input ADCAL ADC State Startup Calibrate 0x00 Calibration factor CALFACT_x[6:0] by S/W by H/W Indicative timings MSv30263V2 Software procedure to re-inject a calibration factor into the ADC Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing).
Page 202 Analog-to-digital converters (ADC) RM0366 Disable the ADC. Calibrate the ADC in single-ended input mode (with ADCALDIF=0). This updates the register CALFACT_S[6:0]. Calibrate the ADC in Differential input modes (with ADCALDIF=1). This updates the register CALFACT_D[6:0]. Enable the ADC, configure the channels and launch the conversions. Each time there is a switch from a single-ended to a differential inputs channel (and vice-versa), the calibration will automatically be injected into the analog ADC.
Page 203 RM0366 Analog-to-digital converters (ADC) Software procedure to enable the ADC Set ADEN=1. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done using the associated interrupt (setting ADRDYIE=1). Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle after the ADCAL bit is cleared by hardware(end of the calibration).
Page 204 Analog-to-digital converters (ADC) RM0366 For all the other control bits of the ADCx_CFGR, ADCx_SMPRx, ADCx_TRx, ADCx_SQRx, ADCx_JDRy, ADCx_OFRy, ADCx_OFCHR and ADCx_IER registers: • For control bits related to configuration of regular conversions, the software is allowed to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion ongoing (ADSTART must be equal to 0).
Page 205 RM0366 Analog-to-digital converters (ADC) 12.3.12 Channel-wise programmable sampling time (SMPR1, SMPR2) Before starting a conversion, the ADC must establish a direct connection between the voltage source under measurement and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the embedded capacitor to the input voltage level.
Page 206 Analog-to-digital converters (ADC) RM0366 Inside the injected sequence, after each conversion is complete: • The converted data are stored into one of the four 16-bit ADCx_JDRy registers • The JEOC (end of injected conversion) flag is set • An interrupt is generated if the JEOCIE bit is set After the regular sequence is complete: •...
Page 207 RM0366 Analog-to-digital converters (ADC) 12.3.15 Starting conversions (ADSTART, JADSTART) Software starts ADC regular conversions by setting ADSTART=1. When ADSTART is set, the conversion starts: • Immediately: if EXTEN = 0x0 (software trigger) • At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0 Software starts ADC injected conversions by setting JADSTART=1.
Page 208 Analog-to-digital converters (ADC) RM0366 Figure 31. Analog-to-digital conversion time ADC state Sampling Ch(N) Converting Ch(N) Sampling Ch(N+1) Analog channel Ch(N) Ch(N+1) Internal S/H Hold AIN(N) Sample AIN(N+1) Sample AIN(N) SMPL Set by ADSTART Cleared Set by by SW EOSMP Cleared by Set by HW/SW ADC_DR...
Page 209 RM0366 Analog-to-digital converters (ADC) Figure 32. Stopping ongoing regular conversions Trigger Trigger Sample Convert Sample ADC state Ch(N-1) Ch(N-1) Ch(N) JADSTART Cleared REGULAR CONVERSIONS ADSTART by SW by HW ongoing (software is not allowed to configure regular conversions selection and triggers) Cleared ADSTP by HW...
Page 210 Analog-to-digital converters (ADC) RM0366 12.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.
Page 211 RM0366 Analog-to-digital converters (ADC) Figure 34. Triggers are shared between ADC master & ADC slave ADC MASTER EXT0 EXTi mapped at EXT1 External regular trigger product level ....EXT15 EXTSEL[3:0] External injected trigger JEXTSEL[3:0] ADC SLAVE External regular trigger EXTSEL[3:0] JEXT0 JEXT1...
Page 212 Analog-to-digital converters (ADC) RM0366 Table 34. ADC1 (master) - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] EXT14 TIM15_TRGO event Internal signal from on chip timers 1110 EXT15 Reserved 1111 Table 35. ADC1 - External trigger for injected channels Name Source Type...
Page 213 RM0366 Analog-to-digital converters (ADC) Note: When using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. For instance, if the sequence length is 28 ADC clock cycles (that is two conversions with a sampling time of 1.5 clock periods), the minimum interval between triggers must be 29 ADC clock cycles.
Page 214 Analog-to-digital converters (ADC) RM0366 12.3.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADCx_CFGR register. It is used to convert a short sequence (sub-group) of n conversions (n ≤ 8) that is part of the sequence of conversions selected in the ADCx_SQR registers.
Page 215 RM0366 Analog-to-digital converters (ADC) Example: • JDISCEN=1, channels to be converted = 1, 2, 3 – 1st trigger: channel 1 converted (a JEOC event is generated) – 2nd trigger: channel 2 converted (a JEOC event is generated) – 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated –...
Page 216 Analog-to-digital converters (ADC) RM0366 hardware or software injected triggers are ignored until the software re-writes a new injected context into JSQR register. • Reading JSQR register returns the current JSQR context which is active at that moment. When the JSQR context is empty, JSQR is read as 0x0000. •...
Page 217 RM0366 Analog-to-digital converters (ADC) Figure 37. Example of JSQR queue of context (trigger change) Write JSQR JSQR queue EMPTY P1,P2 P2,P3 Ignored Trigger 1 Ignored Trigger 2 ADC J context (returned by reading EMPTY JSQR) ADC state Conversion1 Conversion2 Conversion1 MS30537V3 1.
Page 218 Analog-to-digital converters (ADC) RM0366 Figure 39. Example of JSQR queue of context with overflow during conversion => Overflow, ignored Write JSQR JSQR EMPTY P1, P2 P2, P4 queue Cleared by SW JQOVF Trigger 1 Trigger 2 J context EMPTY (returned by reading JSQR) Conversion1 Conversion2...
Page 219 RM0366 Analog-to-digital converters (ADC) Note: When writing P3, the context changes immediately. However, because of internal resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it can happen that the conversion is launched considering the context P2. To avoid this situation, the user must ensure that there is no ADC trigger happening when writing a new context that applies immediately.
Page 220 Analog-to-digital converters (ADC) RM0366 Figure 43. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. Queue is flushed and maintains the last active context (P2 is lost) Write JSQR JSQR EMPTY...
Page 221 RM0366 Analog-to-digital converters (ADC) Figure 45. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) Queue is flushed and becomes empty (P2 is lost) Write JSQR EMPTY EMPTY P1, P2 EMPTY JSQR queue Reset by H/W by S/W JADSTP JADSTART Reset by S/W by H/W...
Page 222 Analog-to-digital converters (ADC) RM0366 Figure 47. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1) Queue is flushed and becomes empty (JSQR is read as 0x0000) JSQR queue P1, P2 EMPTY Reset ADDIS by S/W by H/W ADC J context (returned EMPTY (0x0000) by reading JSQR) ADC state...
Page 223 RM0366 Analog-to-digital converters (ADC) P2: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0) P3: sequence of 1 conversion, software trigger (JEXTEN = 0x0) P4: sequence of 1 conversion, hardware trigger (JEXTEN /= 0x0) Queue of context: Starting the ADC with an empty queue The following procedure must be followed to start ADC operation with an empty queue, in case the first context is not known at the time the ADC is initialized.
Page 224 Analog-to-digital converters (ADC) RM0366 The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if bit EOSMPIE is set. 12.3.24 End of conversion sequence (EOS, JEOS) The ADC notifies the application for each end of regular sequence (EOS) and for each end...
Page 225 RM0366 Analog-to-digital converters (ADC) Figure 50. Continuous conversion of a sequence, software trigger ADCSTART ADSTP ADC state READY CH10 CH17 CH10 READY ADC_DR Indicative timings by SW by HW MS30550V1 1. EXTEN=0x0, CONT=1 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 51.
Page 226 Analog-to-digital converters (ADC) RM0366 12.3.26 Data management Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN) Data and alignment At the end of each regular conversion channel (when EOC event occurs), the result of the converted data is stored into the ADCx_DR data register which is 16 bits wide. At the end of each injected conversion channel (when JEOC event occurs), the result of the converted data is stored into the corresponding ADCx_JDRy data register which is 16 bits wide.
Page 227 RM0366 Analog-to-digital converters (ADC) When reading data from ADCx_DR (regular channel) or from ADCx_JDRy (injected channel, y=1,2,3,4) corresponding to the channel “i”: • If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the read data is signed. •...
Page 228 Analog-to-digital converters (ADC) RM0366 Figure 54. Right alignment (offset enabled, signed value) 12-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT D11 10-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT 8-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT 6-bit data bit15 bit7...
Page 229 RM0366 Analog-to-digital converters (ADC) Figure 56. Left alignment (offset enabled, signed value) 12-bit data bit15 bit7 bit0 SEXT D11 10-bit data bit15 bit7 bit0 SEXT D9 8-bit data bit15 bit7 bit0 SEXT D7 6-bit data bit15 bit7 bit0 SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT MS31018V1 ADC overrun (OVR, OVRMOD)
Page 230 Analog-to-digital converters (ADC) RM0366 Figure 57. Example of overrun (OVR) ADSTART ADSTP TRGx STOP ADC state Overun ADC_DR read access ADC_DR (OVRMOD=0) ADC_DR (OVRMOD=1) by s/w by h/w triggered Indicative timings MS31019V1 Note: There is no overrun detection on the injected channels since there is a dedicated data register for each of the four injected channels.
Page 231 RM0366 Analog-to-digital converters (ADC) corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid. Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section : ADC overrun (OVR, OVRMOD)).
Page 232 Analog-to-digital converters (ADC) RM0366 This is a way to automatically adapt the speed of the ADC to the speed of the system which will read the data. The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after each sequence of injected conversions (whatever JDISCEN=0 or 1).
Page 233 RM0366 Analog-to-digital converters (ADC) Figure 58. AUTODLY=1, regular conversion in continuous mode, software trigger ADSTART (1) ADSTP ADC_DR read access ADC state STOP ADC_DR by SW by HW Indicative timings MS31020V1 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3 3.
Page 234 Analog-to-digital converters (ADC) RM0366 Figure 60. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) Not ignored (occurs during Ignored injected sequence) Regular trigger ADC state RDY CH2 regular regular regular injected injected regular regular DLY (CH1) DLY (CH1) DLY (CH2) DLY (CH3) ADC_DR...
Page 235 RM0366 Analog-to-digital converters (ADC) Figure 61. AUTODLY=1, regular continuous conversions interrupted by injected conversions ADSTART state regular regular regular injected injected regular DLY (CH1) DLY (CH2) DLY (CH3) ADC_DR read access ADC_DR Ignored Injected trigger DLY (inj) JEOS ADC_JDR1 ADC_JDR2 by s/w by h/w Indicative timings...
Page 236 Analog-to-digital converters (ADC) RM0366 12.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 63. Analog watchdog’s guarded area Analog voltage Higher threshold Guarded area Lower threshold...
Page 237 RM0366 Analog-to-digital converters (ADC) These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADCx_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Page 238 Analog-to-digital converters (ADC) RM0366 1. The watchdog comparison is performed on the raw converted data before any alignment calculation and before applying any offsets (the data which is compared is not signed). ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers.
Page 239 RM0366 Analog-to-digital converters (ADC) Figure 65. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7 STATE inside outside inside outside outside outside inside EOC FLAG not cleared by S/W AWDx FLAG ADCy_AWDx_OUT - Converting regular channels 1,2,3,4,5,6,7 - Regular channels 1,2,3,4,5,6,7 are all guarded MS31026V1 Figure 66.
Page 240 To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area.
Page 241 RM0366 Analog-to-digital converters (ADC) Select the ADC1_IN16 input channel (with the appropriate sampling time). Program with the appropriate sampling time (refer to electrical characteristics section of the STM32F3xx datasheet). Set the TSEN bit in the ADC1_CCR register to wake up the temperature sensor from power-down mode.
Page 242 Analog-to-digital converters (ADC) RM0366 Note: The VBATEN bit must be set to enable the conversion of internal channel ADC1_IN17 BATEN 12.3.31 Monitoring the internal voltage reference It is possible to monitor the internal voltage reference (V ) to have a reference point for REFINT evaluating the ADC V voltage level.
Page 243 RM0366 Analog-to-digital converters (ADC) Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done. 12.4 ADC interrupts For each ADC, an interrupt can be generated: •...
Page 244 Analog-to-digital converters (ADC) RM0366 12.5 ADC registers (for each ADC) Refer to Section 1.2 on page 36 for a list of abbreviations used in register descriptions. 12.5.1 ADC interrupt and status register (ADCx_ISR, x=1) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 245 RM0366 Analog-to-digital converters (ADC) Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADCx_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADCx_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
Page 246 Analog-to-digital converters (ADC) RM0366 12.5.2 ADC interrupt enable register (ADCx_IER, x=1) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3 AWD2 AWD1 EOSMP ADRDY Res. Res.
Page 247 RM0366 Analog-to-digital converters (ADC) Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing).
Page 248 Analog-to-digital converters (ADC) RM0366 12.5.3 ADC control register (ADCx_CR, x=1) Address offset: 0x08 Reset value: 0x2000 0000 ADCA ADVREGEN[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LDIF Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 249 RM0366 Analog-to-digital converters (ADC) Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured.
Page 250 Analog-to-digital converters (ADC) RM0366 Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).
Page 251 RM0366 Analog-to-digital converters (ADC) 12.5.4 ADC configuration register (ADCx_CFGR, x=1) Address offset: 0x0C Reset value: 0x0000 00000 JAWD1 AWD1 AWD1S JDISC DISC Res. AWD1CH[4:0] JAUTO DISCNUM[2:0] Res. CONT EXTEN[1:0] EXTSEL[3:0] ALIGN RES[1:0] Res. Bit 31 Reserved, must be kept at reset value. Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection These bits are set and cleared by software.
Page 252 Analog-to-digital converters (ADC) RM0366 Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels 0: Analog watchdog 1 enabled on all channels 1: Analog watchdog 1 enabled on a single channel Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which...
Page 253 RM0366 Analog-to-digital converters (ADC) Bit 14 AUTDLY: Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode. 0: Auto-delayed conversion mode off 1: Auto-delayed conversion mode on Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 254 Analog-to-digital converters (ADC) RM0366 Bit 5 ALIGN: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure : Data register, data alignment and offset (ADCx_DR, OFFSETy, OFFSETy_CH, ALIGN) 0: Right alignment 1: Left alignment Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 255 RM0366 Analog-to-digital converters (ADC) Bits 31:30 Reserved, must be kept at reset value. Bits 29:3 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. 000: 1.5 ADC clock cycles 001: 2.5 ADC clock cycles 010: 4.5 ADC clock cycles...
Page 256 Analog-to-digital converters (ADC) RM0366 12.5.6 ADC sample time register 2 (ADCx_SMPR2, x=1) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1] SMP15_0 SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] Bits 31:27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel.
Page 257 RM0366 Analog-to-digital converters (ADC) Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 12.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 258 Analog-to-digital converters (ADC) RM0366 12.5.9 ADC watchdog threshold register 3 (ADCx_TR3, x=1) Address offset: 0x28 Reset value: 0x00FF 0000 Res. Res. Res. Res. Res. Res. Res. Res. HT3[7:0] Res. Res. Res. Res. Res. Res. Res. Res. LT3[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3.
Page 259 RM0366 Analog-to-digital converters (ADC) 12.5.10 ADC regular sequence register 1 (ADCx_SQR1, x=1) Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4] SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 4th in the regular conversion sequence.
Page 260 Analog-to-digital converters (ADC) RM0366 Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 1st in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 261 RM0366 Analog-to-digital converters (ADC) Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 7th in the regular conversion sequence. Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 262 Analog-to-digital converters (ADC) RM0366 12.5.12 ADC regular sequence register 3 (ADCx_SQR3, x=1) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4] SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence These bits are written by software with the channel number (1..18) assigned as the 14th in the regular conversion sequence.
Page 263 RM0366 Analog-to-digital converters (ADC) 12.5.13 ADC regular sequence register 4 (ADCx_SQR4, x=1) Address offset: 0x3C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SQ16[4:0] Res.
Page 264 Analog-to-digital converters (ADC) RM0366 12.5.14 ADC regular Data Register (ADCx_DR, x=1) Address offset: 0x40 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RDATA[15:0]: Regular Data converted These bits are read-only.
Page 265 RM0366 Analog-to-digital converters (ADC) 12.5.15 ADC injected sequence register (ADCx_JSQR, x=1) Address offset: 0x4C Reset value: 0x0000 0000 Res. JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:2] JSQ2[1:0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[3:0] JL[1:0] Bit 31 Reserved, must be kept at reset value. Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (1..18) assigned as the 4th in the injected conversion sequence.
Page 266 Analog-to-digital converters (ADC) RM0366 Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges...
Page 267 RM0366 Analog-to-digital converters (ADC) 12.5.16 ADC offset register (ADCx_OFRy, x=1) (y=1..4) Address offset: 0x60, 0x64, 0x68, 0x6C Reset value: 0x0000 0000 OFFSETy OFFSETy_CH[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OFFSETy[11:0] Bit 31 OFFSETy_EN: Offset y Enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0].
Page 268 Analog-to-digital converters (ADC) RM0366 12.5.17 ADC injected data register (ADCx_JDRy, x=1, y= 1..4) Address offset: 0x80 - 0x8C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only.
Page 269 RM0366 Analog-to-digital converters (ADC) 12.5.19 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1) Address offset: 0xA4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[18:16] AWD3CH[15:1] Res. Bits 31:19 Reserved, must be kept at reset value. Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection These bits are set and cleared by software.
Page 270 Analog-to-digital converters (ADC) RM0366 Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 DIFSEL[18:16]: Differential mode for channels 18 to 16. These bits are read only. These channels are forced to single-ended input mode (either connected to a single-ended I/O port or to an internal channel).
Page 271 RM0366 Analog-to-digital converters (ADC) 12.6 ADC common registers These registers define the control and status registers common to master and slave ADCs: • One set of registers is related to ADC1 (master) 12.6.1 ADC Common status register (ADCx_CSR, x=1) Address offset: 0x00 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 This register provides an image of the status bits of the different ADCs.
Page 272 Analog-to-digital converters (ADC) RM0366 Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC This bit is a copy of the EOSMP2 bit in the corresponding ADCx_ISR register. Bit 16 ADRDY_SLV: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx_ISR register. Bits 15:11 Reserved, must be kept at reset value.
Page 273 RM0366 Analog-to-digital converters (ADC) 12.6.2 ADC common control register (ADCx_CCR, x=1) Address offset: 0x08 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 VBAT VREF Res. Res. Res. Res. Res. Res. Res. Res.
Page 274 Analog-to-digital converters (ADC) RM0366 Bits 21:18 Reserved, must be kept at reset value. Bits 17:16 CKMODE[1:0]: ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): 00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to Section 7: Reset and clock control (RCC))
Page 275 RM0366 Analog-to-digital converters (ADC) Table 43. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1) (continued) Register name Offset reset value ADCx_CR 0x08 Reset value DISCNUM EXTSEL ADCx_CFGR AWD1CH[4:0] 0x0C [2:0] [3:0] [1:0] Reset value...
Page 276 Analog-to-digital converters (ADC) RM0366 Table 43. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1) (continued) Register name Offset reset value OFFSET2_ ADCx_OFR2 OFFSET2[11:0] CH[4:0] 0x64 Reset value OFFSET3_ ADCx_OFR3 OFFSET3[11:0] CH[4:0] 0x68 Reset value...
Page 277 RM0366 Analog-to-digital converters (ADC) Table 44. ADC register map and reset values (master and slave ADC common registers) offset =0x300, x=1) (continued) Register name Offset reset value 0x04 Reserved Res. ADCx_CCR DELAY[3:0] Res. 0x08 Reset value ADCx_CDR RDATA_SLV[15:0] RDATA_MST[15:0] 0x0C Reset value Refer to Section 2.2 on page 40...
Page 278 Digital-to-analog converter (DAC1) RM0366 Digital-to-analog converter (DAC1) 13.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 279 RM0366 Digital-to-analog converter (DAC1) Figure 70. DAC1 block diagram DAC control register TSELx[2:0] bits SWTRIGx DMAENx TIM6_TRGO TIM2_TRGO TIM15_TRGO EXTI_9 DMA requestx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex LFSRx WAVEx[1:0] bits BOFF 12-bit DORx 12-bit Digital-to-analog DAC1_ _OUT1 converterx MS32651V1 Table 45.
Page 280 Digital-to-analog converter (DAC1) RM0366 13.4 DAC channel enable The DAC channel can be powered on by setting the EN1 bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The EN1 bit enables the analog DAC Channel macrocell only. The DAC Channel digital interface is enabled even if the EN1 bit is reset.
Page 281 RM0366 Digital-to-analog converter (DAC1) Figure 72. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b Independent trigger with single LFSR generation To configure the DAC in this conversion mode (see Section 13.6: Noise generation), the following sequence is required:...
Page 282 Digital-to-analog converter (DAC1) RM0366 13.5.4 DAC trigger selection If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which possible events will trigger conversion as shown in Table Table 46.
Page 283 RM0366 Digital-to-analog converter (DAC1) 13.6 Noise generation In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB clock cycles after each trigger event, following a specific calculation algorithm.
Page 284 Digital-to-analog converter (DAC1) RM0366 13.7 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB clock cycles after each trigger event.
Page 285 RM0366 Digital-to-analog converter (DAC1) 13.8 DMA request The DAC channel has a DMA capability. One DMA channel is used to service DAC channel DMA requests. A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set.
Page 286 Digital-to-analog converter (DAC1) RM0366 13.9 DAC registers Refer to Section 1.2 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 13.9.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 287 RM0366 Digital-to-analog converter (DAC1) Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. 000: Timer 6 TRGO event 001: Reserved 010: Reserved 011: Timer 15 TRGO event 100: Timer 2 TRGO event 101: Reserved 110: EXTI line9 111: Software trigger...
Page 288 Digital-to-analog converter (DAC1) RM0366 13.9.2 DAC software trigger register (DAC_SWTRIGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 289 RM0366 Digital-to-analog converter (DAC1) 13.9.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Bits 31:16 Reserved, must be kept at reset value.
Page 290 Digital-to-analog converter (DAC1) RM0366 Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. 13.9.7 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 Res.
Page 291 RM0366 Digital-to-analog converter (DAC1) 13.9.8 DAC register map Table 47 summarizes the DAC registers. Table 47. DAC register map and reset values Register Offset name DAC_CR 0x00 Reset value DAC_ SWTRIGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0] DHR12L1...
Page 292 Comparator (COMP) RM0366 Comparator (COMP) 14.1 Introduction STM32F3xx devices embed three comparators, COMP2, COMP4 and COMP6 that can be used either as standalone devices (all terminals are available on I/Os) or combined with the timers. The comparators can be used for a variety of functions including: •...
Page 293 RM0366 Comparator (COMP) 14.3 COMP functional description 14.3.1 COMP block diagram The block diagrams of COMP2, COMP4 and COMP6 are shown in following figures: Figure 77. Comparator 2 block diagram COMP2_OUT PA2/PA12/PB9 COMP2_INP COMP interrupt request COMP2 (to EXTI) Polarity selection PA4 (DAC1_CH1) COMP2_INM...
Page 294 Comparator (COMP) RM0366 14.3.2 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers. The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet. The table below summarizes the I/Os that can be used as comparators inputs and outputs.
Page 295 RM0366 Comparator (COMP) There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG. To use a clock source for the comparator, the SYSCFG clock enable control bit must be set in the RCC controller. Important: The polarity selection logic and the output redirection to the port works independently from the PCLK2 clock.
Page 296 Comparator (COMP) RM0366 Figure 80. Comparator output blanking Current limit Current Raw comp output Blanking window Final comp output Comp out Comp out (to TIM_BK …) Blank MS30964V1 14.4 COMP interrupts The comparator outputs are internally connected to the Extended interrupts and events controller.
Page 297 RM0366 Comparator (COMP) Bit 31 COMP2LOCK: Comparator 2 lock This bit is write-once. It is set by software. It can only be cleared by a system reset. It allows to have COMP2_CSR register as read-only. 0: COMP2_CSR is read-write. 1: COMP2_CSR is read-only. Bit 30 COMP2OUT: Comparator 2 output This read-only bit is a copy of comparator 1output state.
Page 298 Comparator (COMP) RM0366 Bits 6:4 COMP2INMSEL[2:0]: Comparator 2 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 2. 000: 1/4 of Vrefint 001: 1/2 of Vrefint 010: 3/4 of Vrefint 011: Vrefint 100: PA4 or DAC1_CH1 output if enabled 110: PA2 Remaining combinations: reserved.
Page 299 RM0366 Comparator (COMP) Bits 20:18 COMP4_BLANKING: Comparator 4 blanking source These bits select which Timer output controls the comparator 4 output blanking. 000: No blanking 011: TIM15 OC1 selected as blanking source Other configurations: reserved, must be kept at reset value Bits 17:16 Reserved, must be kept at reset value.
Page 300 Comparator (COMP) RM0366 COMP COMP6 Res. COMP6OUTSEL[3:0] Res. Res. Res. COMP6INMSEL[2:0] Res. Res. 6POL Bit 31 COMP6LOCK: Comparator 6 lock This bit is write-once. It is set by software. It can only be cleared by a system reset. It allows to have COMP6_CSR register as read-only. 0: COMP6_CSR is read-write.
Page 301 RM0366 Comparator (COMP) Bits 6:4 COMP6INMSEL[2:0]: Comparator 6 inverting input selection These bits allows to select the source connected to the inverting input of the comparator 6. 000: 1/4 of Vrefint 001: 1/2 of Vrefint 010: 3/4 of Vrefint 011: Vrefint 100: PA4 or DAC1_CH1 output if enabled 111: PB15 Remaining combinations: reserved.
Page 302 Comparator (COMP) RM0366 14.5.4 COMP register map The following table summarizes the comparator registers. Table 49. COMP register map and reset values Offset Register COMP2OUT COMP2_CSR SEL[3:0] 0x20 Reset value COMP4OUT COMP4_CSR SEL[3:0] 0x28 Reset value COMP6OUT COMP6_CSR SEL[3:0] 0x30 Reset value Refer to Section 2.2 on page 40...
Page 303 RM0366 Operational amplifier (OPAMP) Operational amplifier (OPAMP) 15.1 OPAMP introduction STM32F3xx devices embed 1 operational amplifier OPAMP2. It can either be used as a standalone amplifier or as a follower / programmable gain amplifier. The operational amplifier output is internally connected to an ADC channel for measurement purposes.
Page 304 Operational amplifier (OPAMP) RM0366 15.3.3 Operational amplifiers and comparators interconnections Internal connections between the operational amplifiers and the comparators are useful in motor control applications. These connections are summarized in the following figures. Figure 81. Comparator and operational amplifier connections PA2/PA12/PB9 COMP interrupt COMP 2...
Page 305 RM0366 Operational amplifier (OPAMP) that causes the OUTCAL bit to change from 1 to 0 in the OPAMP register. If the OUTCAL bit is reset, the offset is calibrated correctly and the corresponding trimming value must be stored. The calibration of the PMOS differential pair is performed in the same way, with two differences: the TRIMOFFSETP bits-fields are used and the CALSEL bits must be programmed to ‘01’...
Page 306 Operational amplifier (OPAMP) RM0366 15.3.7 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes Important note: the amplifier output pin is directly connected to the output pad to minimize the output impedance.
Page 307 RM0366 Operational amplifier (OPAMP) impedance. In this case, the inverting inputs are free and the corresponding ports can be used as regular I/Os. Figure 84. Follower configuration STM32 OpAmp Available I/Os Always connected to OPAMP output (can be used during debug) MS19227V1 1.
Page 308 Operational amplifier (OPAMP) RM0366 Figure 85. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used STM32 OpAmp Available I/Os Always connected to OPAMP output (can be used during debug) MS19228V1 Figure 86. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering STM32 OpAmp...
Page 309 RM0366 Operational amplifier (OPAMP) 15.4 OPAMP registers 15.4.1 OPAMP2 control register (OPAMP2_CSR) Address offset: 0x3C Reset value: 0xXXXX 0000 TSTR USER_ LOCK TRIMOFFSETN TRIMOFFSETP PGA_GAIN TRIM VMS_ TCM_ FORCE OPAMP PGA_GAIN CALSEL VPS_SEL VM_SEL Res. VP_SEL Bit 31 LOCK: OPAMP 2 lock This bit is write-once.
Page 310 Operational amplifier (OPAMP) RM0366 Bits 13:12 CALSEL: Calibration selection This bit is set and cleared by software. It is used to select the offset calibration bus used to generate the internal reference voltage when CALON = 1 or FORCE_VP= 1. 00 = = 3.3% V REFOPAMP...
Page 311 RM0366 Operational amplifier (OPAMP) Bits 3:2 VP_SEL: OPAMP2 non inverting input selection. Theses bits are set/reset by software. They are used to select the OPAMP2 non inverting input. 00: Reserved 01: PB14 used as OPAMP2 non inverting input 10: PB0 used as OPAMP2 non inverting input 11: PA7 used as OPAMP2 non inverting input Bit 1 FORCE_VP: This bit forces a calibration reference voltage on non-inverting input and disables external...
Page 312 Operational amplifier (OPAMP) RM0366 15.4.2 OPAMP register map The following table summarizes the OPAMP registers. Table 51. OPAMP register map and reset values Offset Register OPAMP2_CSR 0x3C Reset value X X X X X X X X X X X X X X X X Refer to Section 2.2 on page 40 for the register boundary addresses.
Page 313 RM0366 Touch sensing controller (TSC) Touch sensing controller (TSC) 16.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode that is protected from direct touch by a dielectric (for example glass, plastic).
Page 314 Touch sensing controller (TSC) RM0366 16.3 TSC functional description 16.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure Figure 87. TSC block diagram SYNC Pulse generator G1_IO1 HCLK Clock G1_IO2 prescalers G1_IO3 Spread spectrum G1_IO4 G2_IO1 G2_IO2...
Page 315 RM0366 Touch sensing controller (TSC) Figure 88. Surface charge transfer analog I/O group structure Analog I/O group Electrode 1 Gx_IO1 SENSOR Gx_IO2 Electrode 2 Gx_IO3 SENSOR Electrode 3 Gx_IO4 SENSOR MSv30930V3 Note: Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected group.
Page 316 Touch sensing controller (TSC) RM0366 Table 52. Acquisition sequence summary Gx_IO1 Gx_IO2 Gx_IO3 Gx_IO4 State State description (channel) (sampling) (channel) (channel) Output open- Input floating drain low with Input floating with analog switch Discharge all C with analog analog switch closed switch closed closed...
Page 317 RM0366 Touch sensing controller (TSC) 16.3.3 Reset and clocks The TSC clock source is the AHB clock (HCLK). Two programmable prescalers are used to generate the pulse generator and the spread spectrum internal clocks: • The pulse generator clock (PGCLK) is defined using the PGPSC[2:0] bits of the TSC_CR register •...
Page 318 Touch sensing controller (TSC) RM0366 The reading of the sampling capacitor I/O, to determine if the voltage across C reached the given threshold, is performed at the end of the pulse low state. Note: The following TSC control register configurations are forbidden: •...
Page 319 RM0366 Touch sensing controller (TSC) 16.3.6 Max count error The max count error prevents long acquisition times resulting from a faulty capacitive sensing channel. It consists of specifying a maximum count value for the analog I/O group counters. This maximum count value is specified using the MCV[2:0] bits in the TSC_CR register.
Page 320 Touch sensing controller (TSC) RM0366 To allow the control of the channel I/O by the TSC peripheral, the corresponding GPIO must be first set to alternate output push-pull mode and the corresponding Gx_IOy bit in the TSC_IOCCR register must be set. For proximity detection where a higher equivalent electrode surface is required or to speed- up the acquisition process, it is possible to enable and simultaneously acquire several channels belonging to the same analog I/O group.
Page 321 RM0366 Touch sensing controller (TSC) In order to improve the system immunity, the Schmitt trigger hysteresis of the GPIOs controlled by the TSC must be disabled by resetting the corresponding Gx_IOy bit in the TSC_IOHCR register. 16.4 TSC low-power modes Table 55.
Page 322 Touch sensing controller (TSC) RM0366 Bits 31:28 CTPH[3:0]: Charge transfer pulse high These bits are set and cleared by software. They define the duration of the high state of the charge transfer pulse (charge of C 0000: 1x t PGCLK 0001: 2x t PGCLK 1111: 16x t...
Page 323 RM0366 Touch sensing controller (TSC) Bits 14:12 PGPSC[2:0]: Pulse generator prescaler These bits are set and cleared by software.They select the AHB clock divider used to generate the pulse generator clock (PGCLK). 000: f HCLK 001: f HCLK 010: f HCLK 011: f HCLK...
Page 324 Touch sensing controller (TSC) RM0366 Bit 2 AM: Acquisition mode This bit is set and cleared by software to select the acquisition mode. 0: Normal acquisition mode (acquisition starts as soon as START bit is set) 1: Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) Note: This bit must not be modified when an acquisition is ongoing.
Page 325 RM0366 Touch sensing controller (TSC) 16.6.3 TSC interrupt clear register (TSC_ICR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 326 Touch sensing controller (TSC) RM0366 16.6.5 TSC I/O hysteresis control register (TSC_IOHCR) Address offset: 0x10 Reset value: 0xFFFF FFFF Res. Res. Res. Res. Res. Res. Res. Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:24 Reserved, must be kept at reset value.
Page 327 RM0366 Touch sensing controller (TSC) 16.6.7 TSC I/O sampling control register (TSC_IOSCR) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:24 Reserved, must be kept at reset value.
Page 328 Touch sensing controller (TSC) RM0366 16.6.9 TSC I/O group control status register (TSC_IOGCSR) Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:22 Reserved, must be kept at reset value.
Page 329 RM0366 Touch sensing controller (TSC) 16.6.11 TSC register map Table 57. TSC register map and reset values Offset Register name CTPH[3:0] CTPL[3:0] SSD[6:0] TSC_CR [2:0] 0x0000 Reset value TSC_IER 0x0004 Reset value TSC_ICR 0x0008 Reset value TSC_ISR 0x000C Reset value TSC_IOHCR 0x0010 Reset value...
Page 330 Touch sensing controller (TSC) RM0366 Table 57. TSC register map and reset values (continued) Offset Register name CNT[13:0] TSC_IOG3CR 0x003C Reset value CNT[13:0] TSC_IOG4CR 0x0040 Reset value CNT[13:0] TSC_IOG5CR 0x0044 Reset value CNT[13:0] TSC_IOG6CR 0x0048 Reset value Refer to Section 2.2: Memory organization for the register boundary addresses.
Page 331 RM0366 Advanced-control timer (TIM1) Advanced-control timer (TIM1) In this section, “TIMx” should be understood as “TIM1” since there is only one instance of this type of timer for the products to which this reference manual applies. 17.1 TIM1 introduction The advanced-control timer (TIM1) consists of a 16-bit auto-reload counter driven by a programmable prescaler.
Page 332 Advanced-control timer (TIM1) RM0366 17.2 TIM1 main features TIM1 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
Page 333 RM0366 Advanced-control timer (TIM1) Figure 92. Advanced-control timer block diagram Internal clock (CK_INT) CK_TIM18 from RCC Trigger ETRF TRGO controller ETRP to other timersto DAC/ADC Polarity selection & edge Input TIMx_ETR detector & prescaler filter ITR0 ITR1 Slave ITR2 Reset, enable, up/down, count TRGI controller ITR3...
Page 334 Advanced-control timer (TIM1) RM0366 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 7.2.7: Clock security system (CSS) A PVD output SRAM parity error signal ®...
Page 335 RM0366 Advanced-control timer (TIM1) 17.3 TIM1 functional description 17.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 336 Advanced-control timer (TIM1) RM0366 Figure 93. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 94.
Page 337 RM0366 Advanced-control timer (TIM1) 17.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 338 Advanced-control timer (TIM1) RM0366 Figure 95. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 34 35 36 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 96. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 339 RM0366 Advanced-control timer (TIM1) Figure 97. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 98. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 340 Advanced-control timer (TIM1) RM0366 Figure 99. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V3 Figure 100.
Page 341 RM0366 Advanced-control timer (TIM1) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 342 Advanced-control timer (TIM1) RM0366 Figure 101. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 03 02 01 00 34 33 32 Counter register Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) MS31184V1 Figure 102. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 343 RM0366 Advanced-control timer (TIM1) Figure 103. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 104. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 344 Advanced-control timer (TIM1) RM0366 Figure 105. Counter timing diagram, update event when repetition counter is not used CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the...
Page 345 RM0366 Advanced-control timer (TIM1) DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 346 Advanced-control timer (TIM1) RM0366 Figure 107. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0003 0002 0001 0000 0001 0002 0003 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 108. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 347 RM0366 Advanced-control timer (TIM1) Figure 109. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 110. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 348 Advanced-control timer (TIM1) RM0366 Figure 111. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register 31 30 2F F8 F9 FA FB FC Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 349 RM0366 Advanced-control timer (TIM1) In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the underflow.
Page 350 Advanced-control timer (TIM1) RM0366 17.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 17.3.5) • trigger for the slave mode (see Section 17.3.25) •...
Page 351 RM0366 Advanced-control timer (TIM1) 17.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 352 Advanced-control timer (TIM1) RM0366 Figure 115. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F Encoder ITRx mode TI1_ED TRGI External clock TI1FP1 CK_PSC mode 1 TI2F_Rising Edge TI2FP2 External clock ETRF Filter detector mode 2 ETRF TI2F_Falling CK_INT Internal clock mode (internal clock) ICF[3:0]...
Page 353 RM0366 Advanced-control timer (TIM1) Figure 116. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 MS31087V2 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR.
Page 354 Advanced-control timer (TIM1) RM0366 As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 355 RM0366 Advanced-control timer (TIM1) 17.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 119 Figure 122 give an overview of one Capture/Compare channel.
Page 356 Advanced-control timer (TIM1) RM0366 Figure 120. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface Input mode Output mode 16/32-bit CC1S[1] Capture/compare preload register CC1S[0] CC1S[1] CC1S[0] Compare IC1PS Capture transfer CC1E OC1PE OC1PE compare shadow register CC1G TIMx_CCMR1 (from time Comparator TIMx_EGR base unit)
Page 357 RM0366 Advanced-control timer (TIM1) Figure 122. Output stage of capture/compare channel (channel 4) TIMx_SMCR OCCS OCREF_CLR To the master mode controller ETRF OC4REFC ocref_clr_int OC4REF ‘0’ Output CNT > CCR4 Output enable Output mode circuit CNT = CCR4 selector controller CC4E CC4P OC3REF...
Page 358 Advanced-control timer (TIM1) RM0366 17.3.7 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 359 RM0366 Advanced-control timer (TIM1) 17.3.8 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 360 Advanced-control timer (TIM1) RM0366 forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register.
Page 361 RM0366 Advanced-control timer (TIM1) shadow register is updated only at the next update event UEV). An example is given in Figure 125. Figure 125. Output compare mode, toggle on OC1 Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B B201...
Page 362 Advanced-control timer (TIM1) RM0366 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 337. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 363 RM0366 Advanced-control timer (TIM1) TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 344. Figure 127 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, •...
Page 364 Advanced-control timer (TIM1) RM0366 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 365 RM0366 Advanced-control timer (TIM1) Figure 128. Generation of 2 phase-shifted PWM signals with 50% duty cycle Counter register OC1REFC CCR1=0 CCR2=8 OC3REFC CCR3=3 CCR4=5 MS33117V1 17.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses.
Page 366 Advanced-control timer (TIM1) RM0366 Figure 129. Combined PWM mode on channel 1 and 3 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 17.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses.
Page 367 RM0366 Advanced-control timer (TIM1) Figure 130. 3-phase combined PWM signals with multiple trigger pulses per period Counter OC5ref OC1refC OC2refC OC3refC Preload Active OC4ref OC6ref TRGO2 MS33102V1 The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals.
Page 368 Advanced-control timer (TIM1) RM0366 Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •...
Page 369 RM0366 Advanced-control timer (TIM1) Figure 133. Dead-time waveforms with delay greater than the positive pulse OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 17.4.20: TIM1 break and dead-time register (TIM1_BDTR) for delay calculation.
Page 370 Advanced-control timer (TIM1) RM0366 The source for BRK_ACTH can be internal only: – A clock failure event generated by the CSS. For further information on the CSS, refer to Section 7.2.7: Clock security system (CSS) – A PVD output ® –...
Page 371 RM0366 Advanced-control timer (TIM1) Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled. If it is enabled, a fail safe clock mode (for example by using the internal PLL and/or the CSS) must be used to guarantee that break events are handled. When one of the breaks occurs (selected level on one of the break inputs): •...
Page 372 Advanced-control timer (TIM1) RM0366 Figure 134. Various output behavior in response to a break event on BKIN (OSSI = 1) BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay...
Page 373 RM0366 Advanced-control timer (TIM1) The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table Note:...
Page 374 Advanced-control timer (TIM1) RM0366 Figure 136. PWM output state following BKIN assertion (OSSI=0) BKIN I/O state defined by the GPIO controller (HI-Z) Deadtime I/O state I/O state defined by the GPIO controller (HI-Z) Active Inactive Disabled MS33104V1 17.3.17 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
Page 375 RM0366 Advanced-control timer (TIM1) Figure 137. Clearing TIMx OCxREF (CCRx) Counter (CNT) ETRF OCxREF (OCxCE = ‘0’) OCxREF (OCxCE = ‘1’) ocref_clr_int ocref_clr_int becomes high still high MS33105V2 Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow.
Page 376 Advanced-control timer (TIM1) RM0366 17.3.18 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 377 RM0366 Advanced-control timer (TIM1) 17.3.19 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 378 Advanced-control timer (TIM1) RM0366 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 379 RM0366 Advanced-control timer (TIM1) Figure 140. Retriggerable one pulse mode TRGI Counter Output MS33106V2 17.3.21 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’...
Page 380 Advanced-control timer (TIM1) RM0366 Table 59. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 381 RM0366 Advanced-control timer (TIM1) Figure 142 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 142. Example of encoder interface mode with TI1FP1 polarity inverted. forward jitter backward jitter forward Counter down down MS33108V1...
Page 382 Advanced-control timer (TIM1) RM0366 17.3.23 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 383 RM0366 Advanced-control timer (TIM1) Example: one wants to change the PWM configuration of the advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
Page 384 Advanced-control timer (TIM1) RM0366 Figure 144. Example of Hall sensor interface TIH1 TIH2 TIH3 Counter (CNT) (CCR2) CCR1 C7A3 C7A8 C794 C7A5 C7AB C796 TRGO=OC2REF OC1N OC2N OC3N Write CCxE, CCxNE and OCxM for next step MS32672V1 384/874 RM0366 Rev 5...
Page 385 RM0366 Advanced-control timer (TIM1) 17.3.25 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 18.3.19: Timer synchronization for details. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 386 Advanced-control timer (TIM1) RM0366 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 387 RM0366 Advanced-control timer (TIM1) register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 388 Advanced-control timer (TIM1) RM0366 In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –...
Page 389 RM0366 Advanced-control timer (TIM1) 17.3.26 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
Page 390 Advanced-control timer (TIM1) RM0366 This is done in the following steps: Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers.
Page 391 RM0366 Advanced-control timer (TIM1) 17.4 TIM1 registers Refer to for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 17.4.1 TIM1 control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res.
Page 392 Advanced-control timer (TIM1) RM0366 Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
Page 393 RM0366 Advanced-control timer (TIM1) Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset.
Page 394 Advanced-control timer (TIM1) RM0366 Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 395 RM0366 Advanced-control timer (TIM1) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 396 Advanced-control timer (TIM1) RM0366 Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of f frequency. A CK_INT prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks.
Page 397 RM0366 Advanced-control timer (TIM1) Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (refer to ETP bit in TIMx_SMCR for tim_etr_in and CCxP/CCxNP bits in TIMx_CCER register for tim_ti1fp1 and tim_ti2fp2).
Page 398 Advanced-control timer (TIM1) RM0366 Bit 13 COMDE: COM DMA request enable 0: COM DMA request disabled 1: COM DMA request enabled Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable...
Page 399 RM0366 Advanced-control timer (TIM1) 17.4.5 TIM1 status register (TIM1_SR) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC6IF CC5IF rc_w0 rc_w0 Res. Res. Res. CC4OF CC3OF CC2OF CC1OF B2IF COMIF CC4IF...
Page 400 Advanced-control timer (TIM1) RM0366 Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected.
Page 401 RM0366 Advanced-control timer (TIM1) 17.4.6 TIM1 event generation register (TIM1_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. COMG CC4G CC3G CC2G CC1G Bits 15:9 Reserved, must be kept at reset value. Bit 8 B2G: Break 2 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 402 Advanced-control timer (TIM1) RM0366 Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 403 RM0366 Advanced-control timer (TIM1) Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC.
Page 404 Advanced-control timer (TIM1) RM0366 corresponding CCxS bits. All the other bits of this register have a different function for input capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). Output compare mode: Res.
Page 405 RM0366 Advanced-control timer (TIM1) Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 406 Advanced-control timer (TIM1) RM0366 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 407 RM0366 Advanced-control timer (TIM1) Bits 11:10 IC4PSC[1:0]: Input capture 4 prescaler Refer to IC1PSC[1:0] description. Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC.
Page 408 Advanced-control timer (TIM1) RM0366 Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode Refer to OC3M[3:0] description. Bit 11 OC4PE: Output compare 4 preload enable Refer to OC1PE description. Bit 10 OC4FE: Output compare 4 fast enable Refer to OC1FE description. Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 409 RM0366 Advanced-control timer (TIM1) Bit 21 CC6P: Capture/Compare 6 output polarity Refer to CC1P description Bit 20 CC6E: Capture/Compare 6 output enable Refer to CC1E description Bits 19:18 Reserved, must be kept at reset value. Bit 17 CC5P: Capture/Compare 5 output polarity Refer to CC1P description Bit 16 CC5E: Capture/Compare 5 output enable Refer to CC1E description...
Page 410 Advanced-control timer (TIM1) RM0366 Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high. 1: OC1N active low. CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description.
Page 411 RM0366 Advanced-control timer (TIM1) Table 61. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 Output disabled (not driven OCxREF + Polarity...
Page 412 Advanced-control timer (TIM1) RM0366 17.4.12 TIM1 counter (TIM1_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Page 413 RM0366 Advanced-control timer (TIM1) 17.4.15 TIM1 repetition counter register (TIM1_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 414 Advanced-control timer (TIM1) RM0366 17.4.17 TIM1 capture/compare register 2 (TIM1_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 415 RM0366 Advanced-control timer (TIM1) 17.4.19 TIM1 capture/compare register 4 (TIM1_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
Page 416 Advanced-control timer (TIM1) RM0366 Bit 24 BK2E: Break 2 enable 0: Break input BRK2 disabled 1: Break input BRK2 enabled Note: The BRK2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 417 RM0366 Advanced-control timer (TIM1) Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 418 Advanced-control timer (TIM1) RM0366 Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 17.4.11: TIM1 capture/compare enable register (TIM1_CCER)).
Page 419 RM0366 Advanced-control timer (TIM1) Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers.
Page 420 Advanced-control timer (TIM1) RM0366 Bits 31:0 DMAB[31:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 421 RM0366 Advanced-control timer (TIM1) Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC6CE: Output compare 6 clear enable Refer to OC1CE description. Bits 24, 14, 13, 12 OC6M[3:0]: Output compare 6 mode Refer to OC1M description.
Page 422 Advanced-control timer (TIM1) RM0366 Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).
Page 423 RM0366 Advanced-control timer (TIM1) 17.4.27 TIM1 register map TIM1 registers are mapped as 16-bit addressable registers as described in the table below: Table 62. TIM1 register map and reset values Offset Register TIM1_CR1 [1:0] [1:0] 0x00 Reset value TIM1_CR2 MMS2[3:0] [2:0] 0x04 Reset value...
Page 424 Advanced-control timer (TIM1) RM0366 Table 62. TIM1 register map and reset values (continued) Offset Register TIM1_CNT CNT[15:0] 0x24 Reset value TIM1_PSC PSC[15:0] 0x28 Reset value TIM1_ARR ARR[15:0] 0x2C Reset value TIM1_RCR REP[15:0] 0x30 Reset value TIM1_CCR1 CCR1[15:0] 0x34 Reset value TIM1_CCR2 CCR2[15:0] 0x38...
Page 425 RM0366 Advanced-control timer (TIM1) Table 62. TIM1 register map and reset values (continued) Offset Register TIM1_CCMR3 OC6M OC5M Output [2:0] [2:0] 0x54 Compare mode Reset value TIM1_CCR5 CCR5[15:0] 0x58 Reset value TIM1_CCR6 CCR6[15:0] 0x5C Reset value Refer to Section 2.2 on page 40 for the register boundary addresses.
Page 426 General-purpose timer (TIM2) RM0366 General-purpose timer (TIM2) 18.1 TIM2 introduction The general-purpose timer TIM2 consists of a 32-bit auto-reload counter driven by a programmable prescaler. The timer may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 427 RM0366 General-purpose timer (TIM2) Figure 149. General-purpose timer block diagram Internal clock (CK_INT) From RCC Trigger ETRF controller TRGO Polarity selection & edge ETRP TIMx_ETR Input filter detector & prescaler to other timers to peripherals ITR0 ITR1 Slave ITR2 TRGI Reset, enable, count controller ITR3...
Page 428 General-purpose timer (TIM2) RM0366 18.3 TIM2 functional description 18.3.1 Time-base unit The main block of the programmable timer is a 32-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 429 RM0366 General-purpose timer (TIM2) Figure 150. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 151.
Page 430 General-purpose timer (TIM2) RM0366 18.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 431 RM0366 General-purpose timer (TIM2) Figure 153. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0000 0002 0003 0034 0035 0036 0001 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 154. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 432 General-purpose timer (TIM2) RM0366 Figure 155. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 156. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 433 RM0366 General-purpose timer (TIM2) Figure 157. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 434 General-purpose timer (TIM2) RM0366 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 158. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 01 00 34 33 32 Counter underflow (cnt_udf) Update event (UEV)
Page 435 RM0366 General-purpose timer (TIM2) Figure 160. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0001 0000 0000 0001 Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31186V1 Figure 161. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 436 General-purpose timer (TIM2) RM0366 Figure 162. Counter timing diagram, Update event CK_PSC Timerclock = CK_CNT 30 2F Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31188V1 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) –...
Page 437 RM0366 General-purpose timer (TIM2) DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 438 General-purpose timer (TIM2) RM0366 Figure 164. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0000 0002 0003 0003 0002 0001 0001 Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31190V1 Figure 165. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 439 RM0366 General-purpose timer (TIM2) Figure 166. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) MS31192V1 Figure 167. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_PSC Timerclock = CK_CNT 05 04 03 02...
Page 440 General-purpose timer (TIM2) RM0366 Figure 168. Counter timing diagram, Update event with ARPE=1 (counter overflow) CK_PSC Timer clock = CK_CNT Counter register F8 F9 FA FB FC 31 30 2F Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active...
Page 441 RM0366 General-purpose timer (TIM2) Figure 169. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register.
Page 442 General-purpose timer (TIM2) RM0366 Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). Note: The capture prescaler is not used for triggering, so it does not need to be configured.
Page 443 RM0366 General-purpose timer (TIM2) Figure 172. External trigger input block TI2F TI1F Encoder mode TRGI External clock CK_PSC mode 1 Divider ETRP External clock ETR pin Filter ETRF /1, /2, /4, /8 mode 2 downcounter CK_INT Internal clock mode ETPS[1:0] ETF[3:0] (internal clock) TIMx_SMCR...
Page 444 General-purpose timer (TIM2) RM0366 Figure 173. Control circuit in external clock mode 2 f CK_INT CNT_EN ETRP ETRF Counter clock = CK_CNT =CK_PSC Counter register MSv33111V3 18.3.4 Capture/Compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 445 RM0366 General-purpose timer (TIM2) Figure 174. Capture/Compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 ICF[3:0] CC1P/CC1NP TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 446 General-purpose timer (TIM2) RM0366 Figure 176. Output stage of Capture/Compare channel (channel 1) TIMx_SMCR OCCS OCREF_CLR To the master mode controller ETRF OC1REFC ocref_clr_int OC1REF ‘0’ Output CNT > CCR1 Output enable Output mode circuit CNT = CCR1 selector controller CC1E CC1P OC2REF...
Page 447 RM0366 General-purpose timer (TIM2) detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 448 General-purpose timer (TIM2) RM0366 For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 449 RM0366 General-purpose timer (TIM2) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 18.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 450 General-purpose timer (TIM2) RM0366 Figure 178. Output compare mode, toggle on OC1 Write B201h in the CC1R register 0039 003A 003B B200 B201 TIM1_CNT 003A B201 TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 18.3.9 PWM mode Pulse width modulation mode permits to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 451 RM0366 General-purpose timer (TIM2) The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Upcounting mode on page 430.
Page 452 General-purpose timer (TIM2) RM0366 compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Center-aligned mode (up/down counting) on page 436.
Page 453 RM0366 General-purpose timer (TIM2) in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 454 General-purpose timer (TIM2) RM0366 18.3.11 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers.
Page 455 RM0366 General-purpose timer (TIM2) Figure 182. Combined PWM mode on channels 1 and 3 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 18.3.12 Clearing the OCxREF signal on an external event The OCxREF signal of a given channel can be cleared when a high level is applied on the ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
Page 456 General-purpose timer (TIM2) RM0366 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Page 457 RM0366 General-purpose timer (TIM2) 18.3.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 458 General-purpose timer (TIM2) RM0366 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 459 RM0366 General-purpose timer (TIM2) Figure 185. Retriggerable one-pulse mode TRGI Counter Output MS33106V2 18.3.15 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Page 460 General-purpose timer (TIM2) RM0366 Table 63. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 461 RM0366 General-purpose timer (TIM2) Figure 187. Example of encoder interface mode with TI1FP1 polarity inverted forward jitter backward jitter forward Counter down down MS33108V1 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. Dynamic information can be obtained (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 462 General-purpose timer (TIM2) RM0366 18.3.18 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 463 RM0366 General-purpose timer (TIM2) Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so it does not need to be configured. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Page 464 General-purpose timer (TIM2) RM0366 CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 465 RM0366 General-purpose timer (TIM2) Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
Page 466 General-purpose timer (TIM2) RM0366 Figure 192. Master/Slave timer example TIM1 TIM2 Clock Master Slave TRGO1 ITR1 CK_PSC mode mode control control Prescaler Counter Prescaler Counter Input trigger selection MS32694V1 Figure 193. Master/slave connection example with 1 channel only timers TIM_mstr TIM_slv Clock Prescaler...
Page 467 RM0366 General-purpose timer (TIM2) Configure TIM1 in master mode so that it outputs a periodic trigger signal on each update event UEV. If MMS=010 is written in the TIM1_CR2 register, a rising edge is output on TRGO each time an update event is generated. To connect the TRGO output of TIM1 to TIM2, TIM2 must be configured in slave mode using ITR0 as internal trigger.
Page 468 General-purpose timer (TIM2) RM0366 In the next example (refer to Figure 195), we synchronize TIM1 and TIM2. TIM1 is the master and starts from 0. TIM2 is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. TIM2 stops when TIM1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register: Configure TIM1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).
Page 469 RM0366 General-purpose timer (TIM2) Configure TIM1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register). Configure the TIM1 period (TIM1_ARR registers). Configure TIM2 to get the input trigger from TIM1 (TS=000 in the TIM2_SMCR register).
Page 470 General-purpose timer (TIM2) RM0366 18.3.20 DMA burst mode The TIMx timers have the capability to generate multiple DMA requests upon a single event. The main purpose is to be able to re-program part of the timer multiple times without software overhead, but it can also be used to read several registers in a row, at regular intervals.
Page 471 RM0366 General-purpose timer (TIM2) 18.3.21 Debug mode ® When the microcontroller enters debug mode (Cortex -M4F core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBGMCU module. For more details, refer to Section 28.15.2: Debug support for timers, watchdog I RM0366 Rev 5...
Page 472 General-purpose timer (TIM2) RM0366 18.4 TIM2 registers In this section, “TIMx” should be understood as “TIM2” since there is only one instance of this type of timer for the products to which this reference manual applies. Refer to Section 1.2 for a list of abbreviations used in register descriptions.
Page 473 RM0366 General-purpose timer (TIM2) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source...
Page 474 General-purpose timer (TIM2) RM0366 Bits 6:4 MMS[2:0]: Master mode selection These bits permit to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
Page 475 RM0366 General-purpose timer (TIM2) 18.4.3 TIM2 slave mode control register (TIM2_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bits 31:17 Reserved, must be kept at reset value. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge...
Page 476 General-purpose timer (TIM2) RM0366 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 477 RM0366 General-purpose timer (TIM2) Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Internal Trigger 3 (ITR3). 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 478 General-purpose timer (TIM2) RM0366 18.4.4 TIM2 DMA/Interrupt enable register (TIM2_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 479 RM0366 General-purpose timer (TIM2) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 480 General-purpose timer (TIM2) RM0366 Bit 1 CC1IF: Capture/compare 1 interrupt flag This flag is set by hardware. It is cleared by software (input capture or output compare mode) or by reading the TIMx_CCR1 register (input capture mode only). 0: No compare match / No input capture occurred 1: A compare match or an input capture occurred If channel CC1 is configured as output: this flag is set when the content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
Page 481 RM0366 General-purpose timer (TIM2) Bit 2 CC2G: Capture/compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 482 General-purpose timer (TIM2) RM0366 Bits 9:8 CC2S[1:0]: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1.
Page 483 RM0366 General-purpose timer (TIM2) 18.4.8 TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for output compare mode (this section) or for input capture mode (previous section). The direction of a channel is defined by configuring the corresponding CCxS bits.
Page 484 General-purpose timer (TIM2) RM0366 Bits 16, 6:4 OC1M[3:0]: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 485 RM0366 General-purpose timer (TIM2) Bit 2 OC1FE: Output compare 1 fast enable This bit decreases the latency between a trigger event and a transition on the timer output. It must be used in one-pulse mode (OPM bit set in TIMx_CR1 register), to have the output pulse starting as soon as possible after the starting trigger.
Page 486 General-purpose timer (TIM2) RM0366 Bits 7:4 IC3F[3:0]: Input capture 3 filter Bits 3:2 IC3PSC[1:0]: Input capture 3 prescaler Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC.
Page 487 RM0366 General-purpose timer (TIM2) Bits 16, 6:4 OC3M[3:0]: Output compare 3 mode Refer to OC1M description (bits 6:4 in TIMx_CCMR1 register) Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 488 General-purpose timer (TIM2) RM0366 Bit 3 CC1NP: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. Bit 2 Reserved, must be kept at reset value.
Page 489 RM0366 General-purpose timer (TIM2) CNT[31:16] CNT[15:0] Bits 31:0 CNT[31:0]: counter value 18.4.13 TIM2 counter [alternate] (TIM2_CNT) Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in TIMx_CR1 register: • Previous section is for UIFREMAP = 0 •...
Page 490 General-purpose timer (TIM2) RM0366 ARR[31:16] ARR[15:0] Bits 31:0 ARR[31:0]: Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 18.3.1: Time-base unit on page 428 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null.
Page 491 RM0366 General-purpose timer (TIM2) Bits 31:0 CCR2[31:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC2PE).
Page 492 General-purpose timer (TIM2) RM0366 Bits 31:0 CCR4[31:0]: Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
Page 493 RM0366 General-purpose timer (TIM2) Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 494 General-purpose timer (TIM2) RM0366 18.4.22 TIMx register map TIMx registers are mapped as described in the table below: Table 66. TIM2 register map and reset values Register Offset name TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0]...
Page 495 RM0366 General-purpose timer (TIM2) Table 66. TIM2 register map and reset values (continued) Register Offset name TIMx_CNT CNT[30:0] 0x24 Reset value TIMx_PSC PSC[15:0] 0x28 Reset value TIMx_ARR ARR[31:0] 0x2C Reset value 0x30 Reserved TIMx_CCR1 CCR1[31:0] 0x34 Reset value TIMx_CCR2 CCR2[31:0] 0x38 Reset value TIMx_CCR3...
Page 496 General-purpose timers (TIM15/TIM16/TIM17) RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.1 TIM15/TIM16/TIM17 introduction The TIM15/TIM16/TIM17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 497 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.3 TIM16/TIM17 main features The TIM16/TIM17 timers include the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 •...
Page 498 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Figure 198. TIM15 block diagram Internal clock (CK_INT) CK_TIM151617 from RCC Trigger controller TRGO to other timers ITR0 Slave ITR1 Reset, enable, count controller ITR2 TRGI mode ITR3 TI1F_ED TI1FP1 TI2FP2 REP register Auto-reload register Repetition Stop, clear or up/down counter CK_PSC...
Page 499 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 199. TIM16/TIM17 block diagram Internal clock (CK_INT) Counter Enable (CEN) To other REP register timers for cross- Auto-reload register trigerring Repetition Stop, clear or up/down counter CK_PSC CK_CNT CNT counter prescaler DTG registers CC1I TIMx_CH1 TI1FP1 Input filter &...
Page 500 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4 TIM15/TIM16/TIM17 functional description 19.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 501 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 200. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 201.
Page 502 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
Page 503 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 202. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timerclock = CK_CNT 34 35 36 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31078V2 Figure 203. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 504 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Figure 204. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31080V2 Figure 205. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register...
Page 505 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 206. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT 05 06 07 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR MS31082V2 Figure 207.
Page 506 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4.3 Repetition counter Section 19.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the...
Page 507 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 208. Update rate examples depending on mode and TIMx_RCR register settings Edge-aligned mode Upcounting Counter TIMx_CNT TIMx_RCR = 0 TIMx_RCR = 1 TIMx_RCR = 2 TIMx_RCR = 3 TIMx_RCR = 3 re-synchronization UEV (by SW) Update Event: preload registers transferred to active registers and update interrupt generated.
Page 508 General-purpose timers (TIM15/TIM16/TIM17) RM0366 only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 209 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Page 509 RM0366 General-purpose timers (TIM15/TIM16/TIM17) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 510 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Figure 212. Capture/compare channel (example: channel 1 input stage) TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 Filter TI1F Edge TI1F_Falling downcounter detector IC1PS Divider TI2FP1 /1, /2, /4, /8 CC1P ICF[3:0] TIMx_CCER TIMx_CCMR1 (from slave mode controller) TI2F_Rising (from channel 2)
Page 511 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 214. Output stage of capture/compare channel (channel 1) To the master mode controller Output OCREF_CLR enable ‘0’ circuit OC1REFC OC1REF OC1_DT CC1P CNT>CCR1 Output Output Dead-time TIM1_CCER mode CNT=CCR1 selector generator controller OC1N_DT Output OC1N ‘0’...
Page 512 General-purpose timers (TIM15/TIM16/TIM17) RM0366 already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when it is written with 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 513 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P and CC1NP bits to ‘0’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected).
Page 514 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: •...
Page 515 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 217. Output compare mode, toggle on OC1 Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B B201 003A TIM1_CCR1 OC1REF= OC1 Match detected on CCR1 Interrupt generated if enabled MS31092V1 19.4.10 PWM mode Pulse Width Modulation mode allows a signal to be generated with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 516 General-purpose timers (TIM15/TIM16/TIM17) RM0366 ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 218 shows some edge- aligned PWM waveforms in an example where TIMx_ARR=8. Figure 218. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8...
Page 517 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 219. Combined PWM mode on channel 1 and 2 OC2’ OC1’ OC1REF OC2REF OC1REF’ OC2REF’ OC1REFC OC1REFC’ OC1REFC = OC1REF AND OC2REF OC1REFC’ = OC1REF’ OR OC2REF’ MS31094V1 19.4.12 Complementary outputs and dead-time insertion The TIM15/TIM16/TIM17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs.
Page 518 General-purpose timers (TIM15/TIM16/TIM17) RM0366 reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: • The OCx output signal is the same as the reference signal except for the rising edge, which is delayed relative to the reference rising edge. •...
Page 519 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Figure 222. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay MS31097V1 The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 19.6.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on page 569 for delay calculation.
Page 520 General-purpose timers (TIM15/TIM16/TIM17) RM0366 The break source can be: • An external source connected to BKIN pin • An internal source: – A clock failure event generated by CSS. For further information on the CSS, refer Section 7.2.7: Clock security system (CSS) –...
Page 521 RM0366 General-purpose timers (TIM15/TIM16/TIM17) active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs (taken over by the GPIO which forces a Hi-Z state) else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 522 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Figure 223. Output behavior in response to a break BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 523 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.4.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus one can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 524 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 525 RM0366 General-purpose timers (TIM15/TIM16/TIM17) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 526 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Figure 226. Retriggerable one pulse mode TRGI Counter Output MS33106V2 19.4.17 UIF bit remapping The IUFREMAP bit in the TIMx_CR1 register forces a continuous copy of the Update Interrupt Flag UIF into bit 31 of the timer counter register (TIMxCNT[31]). This allows both the counter value and a potential roll-over condition signaled by the UIFCPY flag, to be atomically read.
Page 527 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.4.18 Timer input XOR function (TIM15 only) The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 528 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4.19 External trigger synchronization (TIM15 only) The TIM timers are linked together internally for timer synchronization or chaining. The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 529 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we do not need any filter, so we keep IC1F=0000).
Page 530 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we do not need any filter, so we keep IC2F=0000).
Page 531 RM0366 General-purpose timers (TIM15/TIM16/TIM17) The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address).
Page 532 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.4.22 Timer synchronization (TIM15) The TIMx timers are linked together internally for timer synchronization or chaining. Refer to Section 18.3.19: Timer synchronization for details. Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO or the TRGO2 signals must be enabled prior to receive events from the master timer, and the clock frequency (prescaler) must not be changed on-the-fly while triggers are received from the master timer.
Page 533 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.5 TIM15 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 19.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res.
Page 534 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: –...
Page 535 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[2:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 536 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.5.3 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] Res. Res. Res. Res. Res. Res. Res.
Page 537 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (refer to ETP bit in TIMx_SMCR for tim_etr_in and CCxP/CCxNP bits in TIMx_CCER register for tim_ti1fp1 and tim_ti2fp2).
Page 538 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bits 12:10 Reserved, must be kept at reset value. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled...
Page 539 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on the TRG trigger event (active edge detected on TRGI input...
Page 540 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.5.6 TIM15 event generation register (TIM15_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. COMG Res. Res. CC2G CC1G Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 541 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits.
Page 542 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 543 RM0366 General-purpose timers (TIM15/TIM16/TIM17) OC2M OC1M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OC2CE OC2M[2:0] CC2S[1:0] OC1CE OC1M[2:0] CC1S[1:0] Bits 31:25 Reserved, must be kept at reset value. Bits 23:17 Reserved, must be kept at reset value. Bit 15 OC2CE: Output Compare 2 clear enable Bits 24, 14:12 OC2M[3:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable...
Page 544 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 545 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 546 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to CC1P description.
Page 547 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Table 68. Output control bits for complementary OCx and OCxN channels with break feature (TIM15) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 548 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.5.10 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. Bits 30:16 Reserved, must be kept at reset value.
Page 549 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.5.13 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 550 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 551 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bit 14 AOE: Automatic output enable 0: MOE can be set only by software 1: MOE can be set by software or automatically at the next update event (if the break input is not be active) Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 552 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bits 9:8 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK OFF - No bit is write protected 01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written 10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as...
Page 553 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bits 4:0 DBA[4:0]: DMA base address This 5-bit field defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2,...
Page 554 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Table 69. TIM15 register map and reset values (continued) Register Offset name TIM15_DIER 0x0C Reset value TIM15_SR 0x10 Reset value TIM15_EGR 0x14 Reset value TIM15_CCMR1 OC2M CC2S OC1M CC1S Output [2:0] [1:0] [2:0] [1:0] Compare mode Reset value 0x18 TIM15_CCMR1...
Page 555 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Table 69. TIM15 register map and reset values (continued) Register Offset name TIM15_CCR2 CCR2[15:0] 0x38 Reset value LOCK TIM15_BDTR DTG[7:0] [1:0] 0x44 Reset value TIM15_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIM15_DMAR DMAB[15:0] 0x4C Reset value Refer to Section 2.2 on page 40 for the register boundary addresses.
Page 556 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.6 TIM16/TIM17 registers Refer to Section 1.2 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 19.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) Address offset: 0x00 Reset value: 0x0000 UIFRE...
Page 557 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow –...
Page 558 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.
Page 559 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. CC1OF Res. Res. COMIF Res. Res. Res. CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 560 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 561 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.6.6 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) Address offset: 0x18 Reset value: 0x0000 0000 The same register can be used for input capture mode (this section) or for output compare mode (next section). The direction of a channel is defined by configuring the corresponding CCxS bits.
Page 562 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bits 1:0 CC1S[1:0]: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 Others: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’...
Page 563 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bits 16, 6:4 OC1M[3:0]: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 564 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) Address offset: 0x20 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC1NP CC1NE CC1P CC1E Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high...
Page 565 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Bit 2 CC1NE: Capture/Compare 1 complementary output enable 0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits. 1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
Page 566 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Table 70. Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 567 RM0366 General-purpose timers (TIM15/TIM16/TIM17) Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0.
Page 568 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) Address offset: 0x30 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e.
Page 569 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) Address offset: 0x44 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OSSR OSSI LOCK[1:0] DTG[7:0] Note:...
Page 570 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Bit 11 OSSR: Off-state selection for Run mode This bit is used when MOE=1 on channels that have a complementary output which are configured as outputs. OSSR is not implemented if no complementary output is implemented in the timer.
Page 571 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit field defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e.
Page 572 General-purpose timers (TIM15/TIM16/TIM17) RM0366 19.6.17 TIM16 option register (TIM16_OR) Address offset: 0x50 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 573 RM0366 General-purpose timers (TIM15/TIM16/TIM17) 19.6.18 TIM16/TIM17 register map TIM16/TIM17 registers are mapped as 16-bit addressable registers as described in the table below: Table 71. TIM16/TIM17 register map and reset values Register Offset name TIMx_CR1 [1:0] 0x00 Reset value TIMx_CR2 0x04 Reset value TIMx_DIER 0x0C...
Page 574 General-purpose timers (TIM15/TIM16/TIM17) RM0366 Table 71. TIM16/TIM17 register map and reset values (continued) Register Offset name TIMx_RCR REP[7:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIMx_BDTR DTG[7:0] 0x44 [1:0] Reset value TIMx_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIMx_DMAR DMAB[15:0] 0x4C Reset value TI1_...
Page 575 RM0366 Basic timers (TIM6) Basic timers (TIM6) 20.1 TIM6 introduction The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used as generic timers for time base generation but they are also specifically used to drive the digital-to-analog converter (DAC).
Page 576 Basic timers (TIM6) RM0366 20.3 TIM6 functional description 20.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 577 RM0366 Basic timers (TIM6) Figure 232. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timerclock = CK_CNT FA FB Counter register Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter MS31076V2 Figure 233.
Page 578 Basic timers (TIM6) RM0366 20.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 579 RM0366 Basic timers (TIM6) Figure 235. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timerclock = CK_CNT 0000 0002 0003 0034 0035 0036 0001 Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31079V2 Figure 236. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timerclock = CK_CNT...
Page 580 Basic timers (TIM6) RM0366 Figure 237. Counter timing diagram, internal clock divided by N CK_PSC Timerclock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) MS31081V2 Figure 238. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_PSC Timerclock = CK_CNT...
Page 581 RM0366 Basic timers (TIM6) Figure 239. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timerclock = CK_CNT Counter register F1 F2 F3 F4 F5 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 582 Basic timers (TIM6) RM0366 Figure 240. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 33 34 35 36 03 04 05 MS31085V2 20.3.5 Debug mode ® When the microcontroller enters the debug mode (Cortex -M4F core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP...
Page 583 RM0366 Basic timers (TIM6) Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit).
Page 584 Basic timers (TIM6) RM0366 20.4.2 TIM6 control register 2 (TIM6_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res. Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 585 RM0366 Basic timers (TIM6) 20.4.4 TIM6 status register (TIM6_SR) Address offset: 0x10 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event.
Page 586 Basic timers (TIM6) RM0366 Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 20.4.7 TIM6 prescaler (TIM6_PSC)
Page 587 RM0366 Basic timers (TIM6) 20.4.9 TIM6 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 72. TIM6 register map and reset values Register Offset name TIMx_CR1 0x00 Reset value TIMx_CR2 [2:0] 0x04 Reset value 0x08 Reserved...
Page 588 Infrared interface (IRTIM) RM0366 Infrared interface (IRTIM) An infrared interface (IRTIM) for remote control is available on the device. It can be used with an infrared LED to perform remote control functions. It uses internal connections with TIM16, and TIM17 as shown in Figure 241.
Page 589 RM0366 System window watchdog (WWDG) System window watchdog (WWDG) 22.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the down-counter before the T6 bit is cleared.
Page 590 System window watchdog (WWDG) RM0366 22.3.1 WWDG block diagram Figure 242. Watchdog block diagram WWDG CMP = 1 when Register interface T[6:0] > W[6:0] W[6:0] WWDG_CFR wwdg_out_rst WWDG_SR Write to WDGA WWDG_CR readback = 0x40 ? WWDG_CR wwdg_it preload EWIF cnt_out 7-bit down-counter (CNT) WDGTB...
Page 591 RM0366 System window watchdog (WWDG) Figure 243. Window watchdog timing diagram CNT down-counter Refresh not allowed Refresh allowed T[6:0] W[6:0] 0x3F Time WDGTB x 4096 x 2 pclk 0x41 0x40 0x3F wwdg_ewit EWIF = 0 wwdg_rst T6 bit MS47266V1 The formula to calculate the timeout value is given by: WDGTB[1:0] ×...
Page 592 System window watchdog (WWDG) RM0366 22.3.5 Debug mode When the device enters debug mode (processor halted), the WWDG counter either continues to work normally or stops, depending on the configuration bit in DBG module. For more details, refer to . 22.4 WWDG interrupts The early wake-up interrupt (EWI) can be used if specific safety operations or data logging...
Page 593 RM0366 System window watchdog (WWDG) Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter, decremented every [1:0]...
Page 594 System window watchdog (WWDG) RM0366 Bits 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wake-up interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not enabled.
Page 595 RM0366 Independent watchdog (IWDG) Independent watchdog (IWDG) 23.1 Introduction The devices feature an embedded watchdog peripheral (IWDG) that offers a combination of high safety level, timing accuracy, and flexibility of use. This peripheral detects and solves malfunctions due to software failure, and triggers a system reset when the counter reaches a given timeout value.
Page 596 Independent watchdog (IWDG) RM0366 When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000), a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the...
Page 597 RM0366 Independent watchdog (IWDG) 23.3.3 Hardware watchdog If this feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the IWDG key register (IWDG_KR) written by the software before the counter reaches the end of count, and if the downcounter is lower than the window value (WIN[11:0]).
Page 598 Independent watchdog (IWDG) RM0366 23.4 IWDG registers Refer to Section 1.2 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 23.4.1 IWDG key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) Res.
Page 599 RM0366 Independent watchdog (IWDG) 23.4.2 IWDG prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 600 Independent watchdog (IWDG) RM0366 23.4.3 IWDG reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RL[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 601 RM0366 Independent watchdog (IWDG) 23.4.4 IWDG status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 602 Independent watchdog (IWDG) RM0366 23.4.5 IWDG window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WIN[11:0] Bits 31:12 Reserved, must be kept at reset value.
Page 603 RM0366 Independent watchdog (IWDG) 23.4.6 IWDG register map The following table gives the IWDG register map and reset values. Table 74. IWDG register map and reset values Register Offset name IWDG_KR KEY[15:0] 0x00 Reset value IWDG_PR PR[2:0] 0x04 Reset value IWDG_RLR RL[11:0] 0x08...
Page 604 Real-time clock (RTC) RM0366 Real-time clock (RTC) 24.1 Introduction The RTC provides an automatic wake-up to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time- of-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wake-up flag with interrupt capability.
Page 605 RM0366 Real-time clock (RTC) 24.2 RTC main features The RTC unit main features are the following (see Figure 245: RTC block diagram): • Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. •...
Page 606 Real-time clock (RTC) RM0366 24.3 RTC functional description 24.3.1 RTC block diagram Figure 245. RTC block diagram Backup registers RTC_TAMP2 and RTC tamper TAMPxF control registers RTC_TAMP1 RTC_TS Time stamp registers RTC_REFIN HSE/32 RTCCLK ck_apre ck_spre RTC_CALR RTC_PRER RTC_PRER (default 256 Hz) (default 1 Hz) Asynchronous Synchronous...
Page 607 RM0366 Real-time clock (RTC) The RTC includes: • Two alarms • Three tamper events from I/Os – Tamper detection erases the backup registers. • One timestamp event from I/O • Tamper event detection can generate a timestamp event • 16 x 32-bit backup registers –...
Page 608 Real-time clock (RTC) RM0366 Table 75. RTC pin PC13 configuration RTC_ALARM RTC_CALIB RTC_TAMP1 RTC_TS PC13MODE PC13VALUE configuration output output input input and function enabled enabled enabled enabled RTC_ALARM Don’t care Don’t care Don’t care Don’t care output OD RTC_ALARM Don’t care Don’t care Don’t care Don’t care...
Page 609 RM0366 Real-time clock (RTC) 24.3.3 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 7: Reset and clock control (RCC).
Page 610 Real-time clock (RTC) RM0366 register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 1 RTCCLK period. When the application reads the calendar registers, it accesses the content of the shadow registers.
Page 611 RM0366 Real-time clock (RTC) the RTC_ISR register, and the wake-up counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. When the periodic wake-up interrupt is enabled by setting the WUTIE bit in the RTC_CR register, it can exit the device from low-power modes.
Page 612 Real-time clock (RTC) RM0366 When the initialization sequence is complete, the calendar starts counting. Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its Backup domain reset default value (0x00).
Page 613 RM0366 Real-time clock (RTC) read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency. The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers.
Page 614 Real-time clock (RTC) RM0366 (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAFCR), the RTC backup registers (RTC_BKPxR), the wake- up timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR). In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if the reset source is different from the Backup domain reset one (refer to the RTC clock section of the Reset and clock controller for details on the list of RTC clock sources not affected by system reset).
Page 615 RM0366 Real-time clock (RTC) Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned.
Page 616 Real-time clock (RTC) RM0366 causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000); and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800). While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine resolution, the bit CALP can be used to increase the frequency by 488.5 ppm.
Page 617 RM0366 Real-time clock (RTC) Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due to the limitation of the calibration resolution). •...
Page 618 Real-time clock (RTC) RM0366 Optionally, a tamper event can cause a time-stamp to be recorded. See the description of the TAMPTS control bit in Section 24.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR). 24.3.14 Tamper detection The RTC_TAMPx input events can be configured either for edge detection, or for level detection with filtering.
Page 619 RM0366 Real-time clock (RTC) Caution: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with the corresponding TAMPxE bit in order to detect a tamper detection event in case it occurs before the RTC_TAMPx pin is enabled. •...
Page 620 Real-time clock (RTC) RM0366 Note: When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the asynchronous prescaler. When COSEL bit is set, the RTC_CALIB output is the output of the 8th stage of the synchronous prescaler.
Page 621 RM0366 Real-time clock (RTC) Configure and enable the EXTI line corresponding to the RTC Tamper event in interrupt mode and select the rising edge sensitivity. Configure and Enable the RTC_TAMP_STAMP IRQ channel in the NVIC. Configure the RTC to detect the RTC tamper event. To enable the RTC TimeStamp interrupt, the following sequence is required: Configure and enable the EXTI line corresponding to the RTC TimeStamp event in interrupt mode and select the rising edge sensitivity.
Page 622 Bits 14:12 MNT[2:0]: Minute tens in BCD format Bits 11:8 MNU[3:0]: Minute units in BCD format Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format 24.6.2 RTC date register (RTC_DR) The RTC_DR is the calendar date shadow register.
Page 623 RM0366 Real-time clock (RTC) Bits 15:13 WDU[2:0]: Week day units 000: forbidden 001: Monday 111: Sunday Bit 12 MT: Month tens in BCD format Bits 11:8 MU[3:0]: Month units in BCD format Bits 7:6 Reserved, must be kept at reset value. Bits 5:4 DT[1:0]: Date tens in BCD format Bits 3:0 DU[3:0]: Date units in BCD format RM0366 Rev 5...
Page 624 Real-time clock (RTC) RM0366 24.6.3 RTC control register (RTC_CR) Address offset: 0x08 Backup domain reset value: 0x0000 0000 System reset: not affected Res. Res. Res. Res. Res. Res. Res. Res. OSEL[1:0] COSEL SUB1H ADD1H BYPS TSIE WUTIE ALRBIE ALRAIE WUTE ALRBE ALRAE Res.
Page 625 RM0366 Real-time clock (RTC) Bit 16 ADD1H: Add 1 hour (summer time change) When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0. 0: No effect 1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode.
Page 626 Real-time clock (RTC) RM0366 Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz) 0: RTC_REFIN detection disabled 1: RTC_REFIN detection enabled Note: PREDIV_S must be 0x00FF. Bit 3 TSEDGE: Time-stamp event active edge 0: RTC_TS input rising edge generates a time-stamp event 1: RTC_TS input falling edge generates a time-stamp event TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Page 627 RM0366 Real-time clock (RTC) 24.6.4 RTC initialization and status register (RTC_ISR) Address offset: 0x0C Backup domain reset value: 0x0000 0007 System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’ Res. Res. Res. Res. Res. Res.
Page 628 Real-time clock (RTC) RM0366 Bit 8 ALRAF: Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0. Bit 7 INIT: Initialization mode 0: Free running mode 1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER).
Page 629 RM0366 Real-time clock (RTC) Bit 2 WUTWF: Wake-up timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wake-up timer values can be changed when WUTE bit is cleared and WUTWF is set.
Page 630 Real-time clock (RTC) RM0366 24.6.5 RTC prescaler register (RTC_PRER) This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 611. This register is write protected. The write access procedure is described in RTC register write protection on page 611.
Page 631 RM0366 Real-time clock (RTC) 24.6.6 RTC wake-up timer register (RTC_WUTR) This register can be written only when WUTWF is set to 1 in RTC_ISR. This register is write protected. The write access procedure is described in RTC register write protection on page 611.
Page 632 Bit 7 MSK1: Alarm A seconds mask 0: Alarm A set if the seconds match 1: Seconds don’t care in Alarm A comparison Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. 632/874...
Page 633 Bit 7 MSK1: Alarm B seconds mask 0: Alarm B set if the seconds match 1: Seconds don’t care in Alarm B comparison Bits 6:4 ST[2:0]: Second tens in BCD format Bits 3:0 SU[3:0]: Second units in BCD format RM0366 Rev 5...
Page 634 Real-time clock (RTC) RM0366 24.6.9 RTC write protection register (RTC_WPR) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 635 RM0366 Real-time clock (RTC) 24.6.11 RTC shift control register (RTC_SHIFTR) This register is write protected. The write access procedure is described in RTC register write protection on page 611. Address offset: 0x2C Backup domain reset value: 0x0000 0000 System reset: not affected ADD1S Res.
Page 636 Bits 14:12 MNT[2:0]: Minute tens in BCD format. Bits 11:8 MNU[3:0]: Minute units in BCD format. Bit 7 Reserved, must be kept at reset value. Bits 6:4 ST[2:0]: Second tens in BCD format. Bits 3:0 SU[3:0]: Second units in BCD format. 636/874...
Page 637 RM0366 Real-time clock (RTC) 24.6.13 RTC timestamp date register (RTC_TSDR) The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset. Address offset: 0x34 Backup domain reset value: 0x0000 0000 System reset: not affected Res.
Page 638 Real-time clock (RTC) RM0366 24.6.14 RTC time-stamp sub second register (RTC_TSSSR) The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset. Address offset: 0x38 Backup domain reset value: 0x0000 0000 System reset: not affected Res.
Page 639 RM0366 Real-time clock (RTC) 24.6.15 RTC calibration register (RTC_CALR) This register is write protected. The write access procedure is described in RTC register write protection on page 611. Address offset: 0x3C Backup domain reset value: 0x0000 0000 System reset: not affected Res.
Page 640 Real-time clock (RTC) RM0366 24.6.16 RTC tamper and alternate function configuration register (RTC_TAFCR) Address offset: 0x40 Backup domain reset value: 0x0000 0000 System reset: not affected PC15 PC15 PC14 PC14 PC13 PC13 Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 641 RM0366 Real-time clock (RTC) Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs. 0x0: 1 RTCCLK cycle 0x1: 2 RTCCLK cycles 0x2: 4 RTCCLK cycles 0x3: 8 RTCCLK cycles Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count...
Page 642 Real-time clock (RTC) RM0366 Bit 2 TAMPIE: Tamper interrupt enable 0: Tamper interrupt disabled 1: Tamper interrupt enabled. Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input If TAMPFLT != 00 0: RTC_TAMP1 input staying low triggers a tamper detection event. 1: RTC_TAMP1 input staying high triggers a tamper detection event.
Page 643 RM0366 Real-time clock (RTC) 24.6.17 RTC alarm A sub second register (RTC_ALRMASSR) This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode. This register is write protected. The write access procedure is described in RTC register write protection on page 611 Address offset: 0x44...
Page 644 Real-time clock (RTC) RM0366 24.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode. This register is write protected.The write access procedure is described in Section : RTC register write protection.
Page 645 This register is reset on a tamper detection event, as long as TAMPxF=1. 24.6.20 RTC register map Table 80. RTC register map and reset values Register Offset name RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] 0x00 Reset value RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0] 0x04...
Page 646 Real-time clock (RTC) RM0366 Table 80. RTC register map and reset values (continued) Register Offset name RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] 0x1C Reset value RTC_ALRMBR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0] 0x20 Reset value RTC_WPR 0x24 Reset value...
Page 647 RM0366 Real-time clock (RTC) Table 80. RTC register map and reset values (continued) Register Offset name RTC_ OR 0x4C Reset value RTC_BKP0R BKP[31:0] Reset value 0x50 to 0x8C BKP[31:0] RTC_BKP15R Reset value Refer to Section 2.2 on page 40 for the register boundary addresses. RM0366 Rev 5 647/874...
Page 648 Inter-integrated circuit interface (I2C) RM0366 Inter-integrated circuit interface (I2C) 25.1 Introduction The I2C peripheral handles the interface between the device and the serial I²C (inter- integrated circuit) bus. It provides multicontroller capability, and controls all I²C-bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
Page 649 RM0366 Inter-integrated circuit interface (I2C) • Wake-up from Stop mode on address match For information on I2C instantiation, refer to Section 25.3: I2C implementation. 25.3 implementation This section provides an implementation overview with respect to the I2C instantiation. Table 81. I2C implementation I2C features I2C1 I2C2...
Page 650 Inter-integrated circuit interface (I2C) RM0366 25.4.1 I2C block diagram Figure 246. Block diagram I2CCLK i2c_ker_ck Data control Digital Analog Shift register noise noise GPIO I2C_SDA filter filter logic SMBUS generation/ check Wake-up address Clock control match Controller clock Digital Analog generation noise noise...
Page 651 RM0366 Inter-integrated circuit interface (I2C) Table 83. I2C internal input/output signals Internal signal name Signal type Description i2c_ker_ck Input I2C kernel clock, also named I2CCLK in this document i2c_pclk Input I2C APB clock i2c_it Output I2C interrupts, refer to Table 97 for the list of interrupt sources i2c_rx_dma Output...
Page 652 Inter-integrated circuit interface (I2C) RM0366 The following figure shows the transmission of a single byte. The controller generates nine SCL pulses. The transmitter sends the eight data bits to the receiver with the SCL pulses 1 to 8. Then the receiver sends the acknowledge bit to the transmitter with the ninth SCL pulse.
Page 653 RM0366 Inter-integrated circuit interface (I2C) Table 84. Comparison of analog and digital filters Item Analog filter Digital filter Filtering capacity ≥ 50 ns One to fifteen I2CCLK periods – Programmable filtering capacity – Extra filtering capability versus I²C-bus Benefits Available in Stop mode specification requirements –...
Page 654 Inter-integrated circuit interface (I2C) RM0366 Figure 248. Setup and hold timings DATA HOLD TIME SCL falling edge internal detection SDADEL: SCL stretched low by the I2C SYNC1 SDA output delay HD;DAT Data hold time: in case of transmission, the data is sent on SDA output after the SDADEL delay, if it is already available in I2C_TXDR.
Page 655 RM0366 Inter-integrated circuit interface (I2C) Note: and t are only part of the condition when the analog filter is enabled. Refer to AF(min) AF(max) the device datasheet for t values. The t time can at maximum be 3.45 µs for Standard-mode, 0.9 µs for Fast-mode, and HD;DAT 0.45 µs for Fast-mode Plus.
Page 656 Inter-integrated circuit interface (I2C) RM0366 Additionally, in controller mode, the SCL clock high and low levels must be configured by programming the PRESC[3:0], SCLH[7:0], and SCLL[7:0] bitfields of the I2C_TIMINGR register. When the SCL falling edge is internally detected, the I2C peripheral releasing the SCL output after the delay , where .
Page 657 RM0366 Inter-integrated circuit interface (I2C) PE must be kept low during at least three APB clock cycles to perform the I2C reset. To ensure this, perform the following software sequence: Write PE = 0 Check PE = 0 Write PE = 1 25.4.7 I2C data transfer The data transfer is managed through transmit and receive data registers and a shift...
Page 658 Inter-integrated circuit interface (I2C) RM0366 Transmission If the I2C_TXDR register is not empty (TXE = 0), its content is copied into the shift register after the ninth SCL pulse (the acknowledge pulse). Then the shift register content is shifted out on the SDA line. If TXE = 1, which means that no data is written yet in I2C_TXDR, the SCL line is stretched low until I2C_TXDR is written.
Page 659 RM0366 Inter-integrated circuit interface (I2C) When RELOAD = 0 in controller mode, the counter can be used in two modes: • Automatic end (AUTOEND = 1 in the I2C_CR2 register). In this mode, the controller automatically sends a STOP condition once the number of bytes programmed in the NBYTES[7:0] bitfield is transferred.
Page 660 Inter-integrated circuit interface (I2C) RM0366 support clock stretching, I2C must be configured with NOSTRETCH = 1 in the I2C_CR1 register. After receiving an ADDR interrupt, if several addresses are enabled, the user must read the ADDCODE[6:0] bitfield of the I2C_ISR register to check which address matched. The DIR flag must also be checked to know the transfer direction.
Page 661 RM0366 Inter-integrated circuit interface (I2C) Target byte control mode To allow byte ACK control in target reception mode, the target byte control mode must be enabled, by setting the SBC bit of the I2C_CR1 register. This is required to comply with SMBus standards.
Page 662 Inter-integrated circuit interface (I2C) RM0366 Target transmitter A transmit interrupt status (TXIS) flag is generated when the I2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit of the I2C_CR1 register is set. The TXIS flag is cleared when the I2C_TXDR register is written with the next data byte to transmit.
Page 663 RM0366 Inter-integrated circuit interface (I2C) Figure 253. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 Target transmission Target initialization I2C_ISR.ADDR stretched Read ADDCODE and DIR in I2C_ISR Optional: Set I2C_ISR.TXE = 1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS Write I2C_TXDR.TXDATA MSv19851V3 RM0366 Rev 5 663/874...
Page 664 Inter-integrated circuit interface (I2C) RM0366 Figure 254. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 Target transmission Target initialization I2C_ISR.STOPF I2C_ISR.TXIS Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1 and I2C_ISR.TXIS=1 Set I2C_ICR.STOPCF MSv19852V3 664/874 RM0366 Rev 5...
Page 665 RM0366 Inter-integrated circuit interface (I2C) Figure 255. Transfer bus diagrams for I2C target transmitter (mandatory events only) legend: Example I2C target transmitter 3 bytes with 1st data flushed, NOSTRETCH=0: transmission ADDR TXIS TXIS TXIS TXIS reception SCL stretch data3 Address data1 data2 EV4 EV5...
Page 666 Inter-integrated circuit interface (I2C) RM0366 Target receiver The RXNE bit of the I2C_ISR register is set when the I2C_RXDR is full, which generates an interrupt if the RXIE bit of the I2C_CR1 register is set. RXNE is cleared when I2C_RXDR is read.
Page 667 RM0366 Inter-integrated circuit interface (I2C) Figure 257. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 Target reception Target initialization I2C_ISR.RXNE I2C_ISR.STOPF Set I2C_ICR.STOPCF Read I2C_RXDR.RXDATA MSv19856V3 Figure 258. Transfer bus diagrams for I2C target receiver (mandatory events only) Legend Example I2C target receiver 3 bytes, NOSTRETCH = 0: Transmission...
Page 668 Inter-integrated circuit interface (I2C) RM0366 25.4.9 I2C controller mode I2C controller initialization Before enabling the peripheral, the I2C controller clock must be configured, by setting the SCLH and SCLL bits in the I2C_TIMINGR register. The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C Configuration window.
Page 669 RM0366 Inter-integrated circuit interface (I2C) Figure 259. Controller clock generation SCL controller clock generation SCL high level detected SCLH counter starts SCLH SYNC2 SCLL SYNC1 SCL low level detected SCL released SCLL counter starts SCL driven low SCL controller clock synchronization SCL high level detected SCL high level detected SCL high level detected...
Page 670 Inter-integrated circuit interface (I2C) RM0366 Caution: For compliance with the I²C-bus or SMBus specification, the controller clock must respect the timings in the following table. Table 87. I²C-bus and SMBus specification clock timings Standard- Fast-mode Fast-mode SMBus mode (Sm) (Fm) Plus (Fm+) Symbol Parameter...
Page 671 RM0366 Inter-integrated circuit interface (I2C) To launch the communication, set the START bit of the I2C_CR2 register. The controller then automatically sends a START condition followed by the target address, either immediately if the BUSY flag is low, or t time after the BUSY flag transits from high to low state.
Page 672 Inter-integrated circuit interface (I2C) RM0366 If the controller addresses a 10-bit address target, transmits data to this target and then reads data from the same target, a controller transmission flow must be done first. Then a repeated START is set with the 10-bit target address configured with HEAD10R = 1. In this case, the controller sends this sequence: RESTART + Target address 10-bit header Read.
Page 673 RM0366 Inter-integrated circuit interface (I2C) Figure 263. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes Controller transmission Controller initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure target address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = Write I2C_TXDR NBYTES transmitted?
Page 674 Inter-integrated circuit interface (I2C) RM0366 Figure 264. Transfer sequence flow for I2C controller transmitter, N > 255 bytes Controller transmission Controller initialization NBYTES = 0xFF; N=N-255 RELOAD = 1 Configure target address Set I2C_CR2.START I2C_ISR.TXIS I2C_ISR.NACKF = 1? Write I2C_TXDR NBYTES transmitted? I2C_ISR.TC...
Page 675 RM0366 Inter-integrated circuit interface (I2C) Figure 265. Transfer bus diagrams for I2C controller transmitter (mandatory events only) Example I2C controller transmitter 2 bytes, automatic end mode (STOP) legend: TXIS TXIS transmission reception Address data1 data2 SCL stretch INIT EV1 EV2 NBYTES INIT: program target...
Page 676 Inter-integrated circuit interface (I2C) RM0366 Controller receiver In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth SCL pulse. An RXNE event generates an interrupt if the RXIE bit of the I2C_CR1 register is set.
Page 677 RM0366 Inter-integrated circuit interface (I2C) Figure 266. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes Controller reception Controller initialization NBYTES = N AUTOEND = 0 for RESTART; 1 for STOP Configure target address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC =...
Page 678 Inter-integrated circuit interface (I2C) RM0366 Figure 267. Transfer sequence flow for I2C controller receiver, N > 255 bytes Controller reception Controller initialization NBYTES = 0xFF; N=N-255 RELOAD =1 Configure target address Set I2C_CR2.START I2C_ISR.RXNE Read I2C_RXDR NBYTES received? I2C_ISR.TC = Set I2C_CR2.START with target address NBYTES I2C_ISR.TCR...
Page 679 RM0366 Inter-integrated circuit interface (I2C) Figure 268. Transfer bus diagrams for I2C controller receiver (mandatory events only) Example I2C controller receiver 2 bytes, automatic end mode (STOP) RXNE RXNE legend: transmission Address data1 data2 reception INIT SCL stretch NBYTES INIT: program target address, program NBYTES = 2, AUTOEND=1, set START EV1: RXNE ISR: rd data1...
Page 680 Inter-integrated circuit interface (I2C) RM0366 Table 88. Timing settings for of 8 MHz I2CCLK Fast-mode Plus Standard-mode (Sm) Fast-mode (Fm) (Fm+) Parameter 10 kHz 100 kHz 400 kHz 500 kHz PRESC[3:0] SCLL[7:0] 0xC7 0x13 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 7 x 125 ns = 875 ns...
Page 681 RM0366 Inter-integrated circuit interface (I2C) Table 90. Timing settings for of 48 MHz I2CCLK Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+) Parameter 10 kHz 100 kHz 400 kHz 1000 kHz PRESC[3:0] SCLL[7:0] 0xC7 0x13 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 4 x 125 ns = 500 ns...
Page 682 Inter-integrated circuit interface (I2C) RM0366 For more details on these protocols, refer to the SMBus specification (http://smbus.org). STM32CubeMX implements an SMBus stack thanks to X-CUBE-SMBUS, a downloadable software pack that allows basic SMBus configuration per I2C instance. Address resolution protocol (ARP) SMBus target address conflicts can be resolved by dynamically assigning a new unique address to each target device.
Page 683 RM0366 Inter-integrated circuit interface (I2C) appending a packet error code (PEC) at the end of each message transfer. The PEC is calculated by using the C(x) = x + x + 1 CRC-8 polynomial on all the message bytes (including addresses and read/write bits). The I2C peripheral embeds a hardware PEC calculator and allows a not acknowledge to be sent automatically when the received byte does not match the hardware calculated PEC.
Page 684 Inter-integrated circuit interface (I2C) RM0366 Bus idle detection A controller can assume that the bus is free if it detects that the clock and data signals have been high for (max) (refer to the table in Section 25.4.9). > t IDLE HIGH This timing parameter covers the condition where a controller is dynamically added to the...
Page 685 RM0366 Inter-integrated circuit interface (I2C) Table 92. SMBus with PEC configuration Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit Controller Tx/Rx NBYTES + PEC+ STOP Controller Tx/Rx NBYTES + PEC + ReSTART Target Tx/Rx with PEC Timeout detection The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits of the I2C_TIMEOUTR register.
Page 686 Inter-integrated circuit interface (I2C) RM0366 25.4.13 SMBus I2C_TIMEOUTR register configuration examples The following tables provide examples of settings to reach desired t TIMEOUT LOW:SEXT , and t timings at different f frequencies. LOW:MEXT IDLE I2CCLK Table 93. TIMEOUTA[11:0] for maximum t of 25 ms TIMEOUT TIMEOUTA[11:0]...
Page 687 RM0366 Inter-integrated circuit interface (I2C) Figure 270. Transfer sequence flow for SMBus target transmitter N bytes + PEC SMBus target transmission Target initialization I2C_ISR.ADDR = 1? Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = N + 1 PECBYTE = 1 Set I2C_ICR.ADDRCF I2C_ISR.TXIS = 1?
Page 688 Inter-integrated circuit interface (I2C) RM0366 SMBus target receiver When using the I2C peripheral in SMBus mode, set the SBC bit to enable the PEC checking at the end of the programmed number of data bytes. To allow the ACK control of each byte, the reload mode must be selected (RELOAD = 1).
Page 689 RM0366 Inter-integrated circuit interface (I2C) Figure 272. Transfer sequence flow for SMBus target receiver N bytes + PEC SMBus target reception Target initialization I2C_ISR.ADDR = 1? Read ADDCODE and DIR in I2C_ISR stretched I2C_CR2.NBYTES = 1, RELOAD = 1 PECBYTE = 1 Set I2C_ICR.ADDRCF I2C_ISR.RXNE =1? I2C_ISR.TCR = 1?
Page 690 Inter-integrated circuit interface (I2C) RM0366 Figure 273. Bus transfer diagrams for SMBus target receiver (SBC = 1) legend: Example SMBus target receiver 2 bytes + PEC transmission ADDR RXNE RXNE RXNE reception SCL stretch Address data1 data2 NBYTES EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE = 1, RELOAD = 0, set ADDRCF EV2: RXNE ISR: rd data1 EV3: RXNE ISR: rd data2 EV4: RXNE ISR: rd PEC...
Page 691 RM0366 Inter-integrated circuit interface (I2C) When the SMBus controller wants to send a RESTART condition after the PEC, the software mode must be selected (AUTOEND = 0). In this case, once NBYTES[7:0] - 1 are transmitted, the I2C_PECR register content is transmitted. The TC flag is set after the PEC transmission, stretching the SCL line low.
Page 692 Inter-integrated circuit interface (I2C) RM0366 SMBus controller receiver When the SMBus controller wants to receive, at the end of the transfer, the PEC followed by a STOP condition, the automatic end mode can be selected (AUTOEND = 1). The PECBYTE bit must be set and the target address programmed before setting the START bit. In this case, after the receipt of NBYTES[7:0] - 1 data bytes, the next received byte is automatically checked versus the I2C_PECR register content.
Page 693 RM0366 Inter-integrated circuit interface (I2C) Figure 275. Bus transfer diagrams for SMBus controller receiver Example SMBus controller receiver 2 bytes + PEC, automatic end mode (STOP) RXNE RXNE RXNE legend: transmission data1 data2 Address reception INIT SCL stretch NBYTES INIT: program target address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START EV1: RXNE ISR: rd data1 EV2: RXNE ISR: rd data2 EV3: RXNE ISR: rd PEC...
Page 694 Inter-integrated circuit interface (I2C) RM0366 If the received address matches the device own address, I2C stretches SCL low until the device wakes up. The stretch is released when the ADDR flag is cleared by software. Then the transfer goes on normally. If the address does not match, the HSI oscillator is stopped again and the device does not wake up.
Page 695 RM0366 Inter-integrated circuit interface (I2C) Overrun/underrun error (OVR) An overrun or underrun error is detected in target mode when NOSTRETCH = 1 and: • In reception when a new byte is received and the RXDR register has not been read yet. The new received byte is lost, and a NACK is automatically sent as a response to the new byte.
Page 696 Inter-integrated circuit interface (I2C) RM0366 25.5 I2C in low-power modes Table 96. Effect of low-power modes to I2C Mode Description Sleep No effect. I2C interrupts cause the device to exit the Sleep mode. The contents of I2C registers are kept. –...
Page 697 RM0366 Inter-integrated circuit interface (I2C) 25.7 I2C DMA requests 25.7.1 Transmission using DMA DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit of the I2C_CR1 register. Data is loaded from an SRAM area configured through the DMA peripheral (see Section 10: Direct memory access controller (DMA)) to the I2C_TXDR...
Page 698 Inter-integrated circuit interface (I2C) RM0366 25.9 I2C registers Refer to Section 1.2 for the list of abbreviations used in register descriptions. The registers are accessed by words (32-bit). 25.9.1 I2C control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Access: no wait states, except if a write access occurs while a write access is ongoing.
Page 699 RM0366 Inter-integrated circuit interface (I2C) Bit 17 NOSTRETCH: Clock stretching disable This bit is used to disable clock stretching in target mode. It must be kept cleared in controller mode. 0: Clock stretching enabled 1: Clock stretching disabled Note: This bit can be programmed only when the I2C peripheral is disabled (PE = 0). Bit 16 SBC: Target byte control This bit is used to enable hardware byte control in target mode.
Page 700 Inter-integrated circuit interface (I2C) RM0366 Bit 5 STOPIE: STOP detection interrupt enable 0: STOP detection (STOPF) interrupt disabled 1: STOP detection (STOPF) interrupt enabled Bit 4 NACKIE: Not acknowledge received interrupt enable 0: Not acknowledge (NACKF) received interrupts disabled 1: Not acknowledge (NACKF) received interrupts enabled Bit 3 ADDRIE: Address match interrupt enable (target only) 0: Address match (ADDR) interrupts disabled 1: Address match (ADDR) interrupts enabled...
Page 701 RM0366 Inter-integrated circuit interface (I2C) Bit 25 AUTOEND: Automatic end mode (controller mode) This bit is set and cleared by software. 0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low. 1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.
Page 702 Inter-integrated circuit interface (I2C) RM0366 Bit 12 HEAD10R: 10-bit address header only read direction (controller receiver mode) 0: The controller sends the complete 10-bit target address read sequence: START + 2 bytes 10-bit address in write direction + RESTART + first seven bits of the 10-bit address in read direction.
Page 703 RM0366 Inter-integrated circuit interface (I2C) Bit 10 OA1MODE: Own address 1 10-bit mode 0: Own address 1 is a 7-bit address. 1: Own address 1 is a 10-bit address. Note: This bit can be written only when OA1EN = 0. Bits 9:0 OA1[9:0]: Interface own target address 7-bit addressing mode: OA1[7:1] contains the 7-bit own target address.
Page 704 Inter-integrated circuit interface (I2C) RM0366 25.9.5 I2C timing register (I2C_TIMINGR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait states PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0] SCLH[7:0] SCLL[7:0] Bits 31:28 PRESC[3:0]: Timing prescaler This field is used to prescale I2CCLK to generate the clock period t used for data setup PRESC and hold counters (refer to section...
Page 705 RM0366 Inter-integrated circuit interface (I2C) 25.9.6 I2C timeout register (I2C_TIMEOUTR) Address offset: 0x14 Reset value: 0x0000 0000 Access: no wait states, except if a write access occurs while a write access is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed.
Page 706 Inter-integrated circuit interface (I2C) RM0366 25.9.7 I2C interrupt and status register (I2C_ISR) Address offset: 0x18 Reset value: 0x0000 0001 Access: no wait states Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] TIMEO PECER BUSY Res. ALERT ARLO BERR STOPF NACKF ADDR RXNE TXIS Bits 31:24 Reserved, must be kept at reset value.
Page 707 RM0366 Inter-integrated circuit interface (I2C) Bit 9 ARLO: Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE = 0. Bit 8 BERR: Bus error This flag is set by hardware when a misplaced START or STOP condition is detected whereas the peripheral is involved in the transfer.
Page 708 Inter-integrated circuit interface (I2C) RM0366 Bit 0 TXE: Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR.
Page 709 RM0366 Inter-integrated circuit interface (I2C) 25.9.9 I2C PEC register (I2C_PECR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 710 Inter-integrated circuit interface (I2C) RM0366 25.9.11 I2C transmit data register (I2C_TXDR) Address offset: 0x28 Reset value: 0x0000 0000 Access: no wait states Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 711 RM0366 Inter-integrated circuit interface (I2C) 25.9.12 I2C register map The table below provides the I2C register map and the reset values. Table 98. I2C register map and reset values Offset Register name I2C_CR1 DNF[3:0] 0x00 Reset value I2C_CR2 NBYTES[7:0] SADD[9:0] 0x04 Reset value I2C_OAR1...
Page 712 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) 26.1 Introduction The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of Full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a programmable baud rate generator.
Page 713 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) • Communication control/error detection flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Fourteen interrupt sources with flags • Multiprocessor communications The USART enters mute mode if the address does not match. •...
Page 714 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 26.4 USART implementation Table 99. STM32F3xx USART features USART2/ USART modes/features USART1 USART3 Hardware flow control for modem Continuous communication using DMA Multiprocessor communication Synchronous mode Smartcard mode Single-wire half-duplex communication IrDA SIR ENDEC block LIN mode Dual clock domain and wake-up from Stop mode Receiver timeout interrupt...
Page 715 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Serial data are transmitted and received through these pins in normal USART mode. The frames are comprised of: • An Idle Line prior to transmission or reception • A start bit • A data word (7, 8 or 9 bits) least significant bit first •...
Page 716 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 276. USART block diagram PRDATA PWDATA Write Read DR (data register) (CPU or DMA) (CPU or DMA) Transmit shift register Receive shift register IrDA Transmit data register Receive data register ENDEC (TDR) (RDR) block USART_GTPR register CK control...
Page 717 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) 26.5.1 USART character description The word length can be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits in the USART_CR1 register (see Figure 277). • 7-bit character length: M[1:0] = 10 •...
Page 718 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 277. Word length programming 9-bit word length (M = 01 ), 1 Stop bit Possible Data frame Parity Next Start Stop Start Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Clock Start Idle frame Stop Stop...
Page 719 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) 26.5.2 USART transmitter The transmitter can send data words of either 7, 8 or 9 bits depending on the M bits status. The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Page 720 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 278. Configurable stop bits 8-bit data, 1 Stop bit Possible Data frame Next Next data frame parity bit start Stop Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK ** LBCL bit controls last data clock pulse 8-bit data, 1 1/2 Stop bits Possible Data frame...
Page 721 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) When no transmission is taking place, a write instruction to the USART_TDR register places the data in the shift register, the data transmission starts, and the TXE bit is set. If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An interrupt is generated if the TCIE bit is set in the USART_CR1 register.
Page 722 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Start bit detection The start bit detection sequence is the same when oversampling by 16 or by 8. In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.
Page 723 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Character reception During an USART reception, data shifts in least significant bit first (default configuration) through the RX pin. In this mode, the USART_RDR register consists of a buffer (RDR) between the internal bus and the receive shift register. Character reception procedure Program the M bits in USART_CR1 to define the word length.
Page 724 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Overrun error An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.
Page 725 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 281 Figure 282). Depending on the application: •...
Page 726 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 281. Data sampling when oversampling by 16 RX line sampled values Sample clock 6/16 7/16 7/16 One bit time MSv31152V1 Figure 282. Data sampling when oversampling by 8 RX line sampled values Sample clock (x8) One bit time MSv31153V1...
Page 727 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Framing error A framing error is detected when the stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise. When the framing error is detected: • The FE bit is set by hardware •...
Page 728 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 26.5.4 USART baud rate generation The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the USART_BRR register. Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1) In case of oversampling by 16, the equation is: Tx/Rx baud --------------------------------...
Page 729 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Example 2 To obtain 921.6 kbaud with f = 48 MHz. • In case of oversampling by 16: USARTDIV = 48 000 000/921 600 BRR = USARTDIV = 52d = 34h • In case of oversampling by 8: USARTDIV = 2 * 48 000 000/921 600 USARTDIV = 104 (104d = 68h) BRR[3:0] = USARTDIV[3:0] >>...
Page 730 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 26.5.5 Tolerance of the USART receiver to clock deviation The asynchronous receiver of the USART works correctly only if the total clock system deviation is less than the tolerance of the USART receiver. The causes which contribute to the total deviation are: •...
Page 731 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Table 102. Tolerance of the USART receiver when BRR [3:0] = 0000 OVER8 bit = 0 OVER8 bit = 1 M bits ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1 3.75% 4.375% 2.50% 3.75% 3.41% 3.97% 2.27% 3.41% 4.16% 4.86% 2.77%...
Page 732 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 start bit (BRs), then at the end of bit 6 (based on the measurement done from falling edge to falling edge: BR6). Bit 0 to bit 6 are sampled at BRs while further bits of the character are sampled at BR6.
Page 733 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) In mute mode: • None of the reception status bits can be set. • All the receive interrupts are inhibited. • The RWU bit in USART_ISR register is set to 1. RWU can be controlled automatically by hardware or by software, through the MMRQ bit in the USART_RQR register, under certain conditions.
Page 734 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 The USART enters mute mode when an address character is received which does not match its programmed address. In this case, the RWU bit is set by hardware. The RXNE flag is not set for this address byte and no interrupt or DMA request is issued when the USART enters mute mode.
Page 735 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Modbus/ASCII In this mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function. By programming the LF ASCII code in the ADD[7:0] field and by activating the character match interrupt (CMIE=1), the software is informed when a LF has been received and can check the CR/LF in the DMA buffer.
Page 736 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Parity generation in transmission If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=0) or an odd number of “1s”...
Page 737 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Examples of break frames are given on Figure 286: Break detection in LIN mode vs. Framing error detection on page 738. Figure 285. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough =>...
Page 738 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 286. Break detection in LIN mode vs. Framing error detection Case 1: break occurring after an Idle RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header) 1 data time 1 data time RXNE /FE LBDF Case 2: break occurring while data is being received...
Page 739 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR written). This means that it is not possible to receive synchronous data without transmitting data.
Page 740 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 289. USART data clock timing diagram (M bits = 01) Idle or Idle or next preceding Start M bits =01 (9 data bits) Stop transmission transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1)
Page 741 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) 26.5.12 USART single-wire half-duplex communication Single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3 register. In this mode, the following bits must be kept cleared: • LINEN and CLKEN bits in the USART_CR2 register, •...
Page 742 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 291. ISO 7816-3 asynchronous protocol Without Parity error Guard time Start bit WithParity error Guard time Start bit Line pulled low by receiver during stop in case of parity error MSv31162V1 When connected to a smartcard, the TX output of the USART drives a bidirectional line that is also driven by the smartcard.
Page 743 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) • In transmission, the USART inserts the Guard Time (as programmed in the Guard Time register) between two successive characters. As the Guard Time is measured after the stop bit of the previous character, the GT[7:0] register must be programmed to the desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12 (the duration of one character).
Page 744 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Block mode (T=1) In T=1 (block) mode, the parity error transmission is deactivated, by clearing the NACK bit in the UART_CR3 register. When requesting a read from the smartcard, in block mode, the software must enable the receiver Timeout feature by setting the RTOEN bit in the USART_CR2 register and program the RTO bits field in the RTOR register to the BWT (block wait time) - 11 value.
Page 745 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Direct and inverse convention The smartcard protocol defines two conventions: direct and inverse. The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state of the line and parity is even. In order to use this convention, the following control bits must be programmed: MSBFIRST=0, DATAINV=0 (default values).
Page 746 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 If none of the two is recognized, a card reset may be generated in order to restart the negotiation. 26.5.14 USART IrDA SIR ENDEC block This section is relevant only when IrDA mode is supported. Please refer to Section 26.4: USART implementation on page 714.
Page 747 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) IrDA low-power mode Transmitter In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally, this value is 1.8432 MHz (1.42 MHz <...
Page 748 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 26.5.15 USART continuous communication in DMA mode The USART is capable of performing continuous communication using the DMA. The DMA requests for Rx buffer and Tx buffer are generated independently. Note: Please refer to Section 26.4: USART implementation on page 714 to determine if the DMA mode is supported.
Page 749 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Figure 295. Transmission using DMA Idle preamble Frame 2 Frame 1 Frame 3 TX line Set by hardware Set by hardware TXE flag cleared by DMA read Set by hardware cleared by DMA read Ignored by the DMA because DMA request the transfer is complete...
Page 750 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 296. Reception using DMA Frame 1 Frame 2 Frame 3 TX line Set by hardware RXNE flag cleared by DMA read DMA request USART_RDR DMA reads USART_RDR Cleared DMA TCIF flag Set by hardware (transfer complete) software Software configures the...
Page 751 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and CTSE bits respectively to 1 (in the USART_CR3 register). RS232 RTS flow control If the RTS flow control is enabled (RTSE=1), then RTS is deasserted (tied low) as long as the USART receiver is ready to receive a new data.
Page 752 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Figure 299. RS232 CTS flow control Transmit data register Data 2 empty Data 3 empty Stop Start Stop Start Idle Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until CTS = 0 MSv68793V1 Note:...
Page 753 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Note: If the USART kernel clock is kept on during Stop mode, there is no constraint on the maximum baud rate that allows waking up from Stop mode. It is the same as in Run mode. •...
Page 754 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 In these conditions, according to Table 102: Tolerance of the USART receiver when BRR [3:0] = 0000, the USART receiver tolerance is 4.86 %. DTRA + DQUANT + DREC + DTCL + DWU < USART receiver's tolerance DWU max = t / (9 x Tbit Min) WUUSART...
Page 755 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Table 106. USART interrupt requests (continued) Enable Control Interrupt event Event flag Noise Flag, Overrun error and Framing Error in multibuffer NF or ORE or FE communication. Character match CMIE Receiver timeout RTOF RTOIE End of Block EOBF EOBIE...
Page 756 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 26.8 USART registers Refer to Section 1.2 on page 36 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32 bits). 26.8.1 USART control register 1 (USART_CR1) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 757 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time This 5-bit value defines the time between the end of the last stop bit, in a transmitted message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
Page 758 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bit 8 PEIE: PE interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever PE=1 in the USART_ISR register Bit 7 TXEIE: interrupt enable This bit is set and cleared by software.
Page 759 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 2 RE: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 UESM: USART enable in Stop mode When this bit is cleared, the USART is not able to wake up the MCU from Stop mode.
Page 760 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bits 31:28 ADD[7:4]: Address of the USART node This bit-field gives the address of the USART node or a character code to be recognized. This is used in multiprocessor communication during mute mode or Stop mode, for wake-up with 7- bit address mark detection.
Page 761 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 18 DATAINV: Binary data inversion This bit is set and cleared by software. 0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) 1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted.
Page 762 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bit 11 CLKEN: Clock enable This bit allows the user to enable the CK pin. 0: CK pin disabled 1: CK pin enabled This bit can only be written when the USART is disabled (UE=0). Note: If neither synchronous mode nor smartcard mode is supported, this bit is reserved and must be kept at reset value.
Page 763 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 5 LBDL: LIN break detection length This bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection This bit can only be written when the USART is disabled (UE=0). Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value.
Page 764 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bits 21:20 WUS[1:0]: Wake-up from Stop mode interrupt flag selection This bit-field specify the event which activates the WUF (wake-up from Stop mode flag). 00: WUF active on address match (as defined by ADD[7:0] and ADDM7) 01:Reserved.
Page 765 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 12 OVRDIS: Overrun Disable This bit is used to disable the receive overrun detection. 0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data. 1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the USART_RDR register.
Page 766 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bit 5 SCEN: Smartcard mode enable This bit is used for enabling smartcard mode. 0: Smartcard mode disabled 1: Smartcard mode enabled This bit field can only be written when the USART is disabled (UE=0). Note: If the USART does not support smartcard mode, this bit is reserved and must be kept at reset value.
Page 767 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) 26.8.4 USART baud rate register (USART_BRR) This register can only be written when the USART is disabled (UE=0). It may be automatically updated by hardware in auto baud rate detection mode. Address offset: 0x0C Reset value: 0x0000 0000 Res.
Page 768 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 GT[7:0]: Guard time value This bit-field is used to program the Guard time value in terms of number of baud clock periods. This is used in smartcard mode. The Transmission Complete flag is set after this guard time value.
Page 769 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bits 31:24 BLEN[7:0]: Block Length This bit-field gives the Block length in smartcard T=1 Reception. Its value equals the number of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1. Examples: BLEN = 0 ->...
Page 770 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bits 31:5 Reserved, must be kept at reset value. Bit 4 TXFRQ: Transmit data flush request Writing 1 to this bit sets the TXE flag. This allows to discard the transmit data. This bit must be used only in smartcard mode, when data has not been sent due to errors (NACK) and the FE flag is active in the USART_ISR register.
Page 771 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bits 31:26 Reserved, must be kept at reset value. Bit 25 TCBGT: Transmission complete before guard time completion. This bit is used in smartcard mode. It is set by hardware if the transmission of a frame containing data has completed successfully (no NACK received from the card) and before the guard time has elapsed (contrary to the TC flag which is set when the guard time has elapsed).
Page 772 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bit 17 CMF: Character match flag This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared by software, writing 1 to the CMCF in the USART_ICR register. An interrupt is generated if CMIE=1in the USART_CR1 register.
Page 773 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 11 RTOF: Receiver timeout This bit is set by hardware when the timeout value, programmed in the RTOR register has lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in the USART_ICR register.
Page 774 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bit 6 TC: Transmission complete This bit is set by hardware if the transmission of a frame containing data is complete and if TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR register.
Page 775 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Bit 2 NF: START bit Noise detection flag This bit is set by hardware when noise is detected on a received frame. It is cleared by software, writing 1 to the NFCF bit in the USART_ICR register. 0: No noise is detected 1: Noise is detected Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit...
Page 776 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 Bit 12 EOBCF: End of block clear flag Writing 1 to this bit clears the EOBF flag in the USART_ISR register. Note: If the USART does not support smartcard mode, this bit is reserved and must be kept at reset value.
Page 777 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) 26.8.10 USART receive data register (USART_RDR) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 778 Universal synchronous/asynchronous receiver transmitter (USART/UART) RM0366 26.8.12 USART register map The table below gives the USART register map and reset values. Table 107. USART register map and reset values Register Offset name reset value USART_CR1 0x00 Reset value STOP USART_CR2 ADD[7:4] ADD[3:0] [1:0]...
Page 779 RM0366 Universal synchronous/asynchronous receiver transmitter (USART/UART) Table 107. USART register map and reset values (continued) Register Offset name reset value USART_TDR TDR[8:0] 0x28 Reset value X X X X X X X X X Refer to Section 2.2 on page 40 for the register boundary addresses.
Page 780 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) 27.1 Introduction The SPI/I²S interface can be used to communicate with external devices using the SPI protocol or the I S audio protocol. SPI or I S mode is selectable by software.
Page 781 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) 27.3 I2S main features • Full-duplex communication • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) •...
Page 782 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 27.5 SPI functional description 27.5.1 General description The SPI allows synchronous, serial communication between the MCU and external devices. Application software can manage the communication by polling the status flag or using dedicated SPI interrupt.
Page 783 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) 27.5.2 Communications between one master and one slave The SPI allows the MCU to communicate using different configurations, depending on the device targeted and the application requirements. These configurations use 2 or 3 wires (with software NSS management) or 3 or 4 wires (with hardware NSS management).
Page 784 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 303. Half-duplex single master/ single slave application MISO MISO Rx shift register Tx shift register MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave MSv39624V1 1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the pins can be left unused by the peripheral.
Page 785 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Figure 304. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) MISO MISO Rx shift register Tx shift register MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave...
Page 786 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 305. Master and three independent slaves MISO MISO Rx shift register Tx shift register MOSI MOSI Tx shift register Rx shift register SPI clock generator Master Slave 1 MISO Tx shift register MOSI Rx shift register Slave 2...
Page 787 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) If potentially both nodes raised their mastering request at the same time a bus conflict event appears (see mode fault MODF event). Then the user can apply some simple arbitration process (e.g. to postpone next attempt by predefined different time-outs applied at both nodes).
Page 788 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 307. Hardware/software slave select management SSI control bit SSM control bit Master Slave mode Inp. mode Non active Conflict Active NSS Input GPIO logic NSS Output Output (used in Master mode and NSS Control HW management only) SSOE control bit...
Page 789 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Figure 308, shows an SPI full-duplex transfer with the four combinations of the CPHA and CPOL bits. Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit. The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
Page 790 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 309. Data alignment when data length is not equal to 8-bit or 16-bit DS <= 8 bits: data is right-aligned on byte DS > 8 bits: data is right-aligned on 16 bit Example: DS = 5 bit Example: DS = 14 bit Data frame...
Page 791 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Note: (1) Step is not required in slave mode. (2) Step is not required in TI mode. (3) Step is not required in NSSP mode. (4) The step is not required in slave mode except slave working at TI mode 27.5.8 Procedure for enabling SPI It is recommended to enable the SPI slave before the master sends the clock.
Page 792 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Another way to manage the data exchange is to use DMA (see Communication using DMA (direct memory addressing)). If the next data is received when the RXFIFO is full, an overrun event occurs (see description of OVR flag at Section 27.5.10: SPI status flags).
Page 793 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) the SPI is disabled at the master transmitter while a frame transaction is ongoing or next data frame is stored in TXFIFO, the SPI behavior is not guaranteed. When the master is in any receive only mode, the only way to stop the continuous clock is to disable the peripheral by SPE=0.
Page 794 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 RxFIFO threshold setting and the following read access must be always kept aligned at the receiver side, as data can be lost if it is not in line. A specific problem appears if an odd number of such “fit into one byte” data frames must be handled.
Page 795 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) When starting communication using DMA, to prevent DMA channel management raising error events, these steps must be followed in order: Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is used.
Page 796 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Communication diagrams Some typical timing schemes are explained in this section. These schemes are valid no matter if the SPI events are handled by polling, interrupts or DMA. For simplicity, the LSBFIRST=0, CPOL=0 and CPHA=1 setting is used as a common assumption here.
Page 797 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Figure 311. Master full-duplex communication MOSI DTx1 DTx2 DTx3 Enable Tx/Rx DMA or interrupts DTx2 DTx3 DTx1 DMA or software control at Tx events FTLVL DRx1 DRx2 DRx3 MISO RXNE DMA or software control at Rx events DRx1 DRx2 DRx3...
Page 798 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 312. Slave full-duplex communication MISO DTx1 DTx2 DTx3 Enable Tx/Rx DMA or interrupts DTx1 DTx2 DTx3 DMA or software control at Tx events FTLVL DRx1 DRx2 DRx3 MOSI RXNE DMA or software control at Rx events DRx1 DRx2 DRx3...
Page 799 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Figure 313. Master full-duplex communication with CRC MOSI DTx1 DTx2 Enable Tx/Rx DMA or interrupts DTx2 DTx1 DMA or software control at Tx events FTLVL DRx1 DRx2 MISO RXNE DMA or software control at Rx events DRx1 DRx2 DRx3...
Page 800 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 314. Master full-duplex communication in packed mode DTx1-2 DTx3-4 DTx5 MOSI 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 Enable Tx/Rx DMA or interrupts DTx1-2 DTx3-4...
Page 801 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) 27.5.10 SPI status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) The TXE flag is set when transmission TXFIFO has enough space to store data to send. TXE flag is linked to the TXFIFO level.
Page 802 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 27.5.11 SPI error flags An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled by setting the ERRIE bit. Overrun flag (OVR) An overrun condition occurs when data is received by a master or slave and the RXFIFO has not enough space to store this received data.
Page 803 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt is generated on the NSS error detection. In this case, the SPI should be disabled because data consistency is no longer guaranteed and communications should be reinitiated by the master when the slave SPI is enabled again.
Page 804 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the formula: baud_rate baud_rate × < < × --------------------- - --------------------- - pclk release pclk If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is set.
Page 805 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Note: The polynomial value should only be odd. No even values are supported. CRC transfer managed by CPU Communication starts and continues normally until the last data frame has to be sent or received in the SPIx_DR register.
Page 806 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 If the SPI is disabled during a communication the following sequence must be followed: Disable the SPI Clear the CRCEN bit Enable the CRCEN bit Enable the SPI Note: When the SPI interface is configured as a slave, the NSS internal signal needs to be kept low during transaction of the CRC phase once the CRCNEXT signal is released.
Page 807 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) 27.7 I2S functional description 27.7.1 I2S general description The block diagram of the I2S is shown in Figure 317. Figure 317. I2S block diagram Address and data bus Tx buffer BSY OVR MODF TxE RxNE SIDE 16-bit...
Page 808 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 The I2S shares three common pins with the SPI: • SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in half-duplex mode only). •...
Page 809 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) I2Sx can operate in master mode. As a result: • Only I2Sx can output SCK and WS in half-duplex mode • Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full-duplex mode. The extended I2Ss (I2Sx_ext) can be used only in full-duplex mode.
Page 810 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 319. I S Philips protocol waveforms (16/32-bit full accuracy) transmission reception Can be 16-bit or 32-bit Channel left Channel right MS19591V1 Data are latched on the falling edge of CK (for the transmitter) and are read on the rising edge (for the receiver).
Page 811 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Figure 322. Receiving 0x8EAA33 First read to Data register Second read to Data register 0x8EAA 0x33XX Only the 8 MSB are sent to compare the 24 bits 8 LSBs have no meaning and can be anything MS19594V1 Figure 323.
Page 812 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 325. MSB Justified 16-bit or 32-bit full-accuracy length Transmission Reception 16- or 32 bit data Channel left Channel right MS30100 V1 Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge (for the receiver).
Page 813 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Figure 328. LSB justified 16-bit or 32-bit full-accuracy Transmission Reception 16- or 32-bit data Channel left Channel right MS30103V1 Figure 329. LSB justified 24-bit frame length Reception Transmission 8-bit data 24-bit remaining 0 forced Channel left 32-bit Channel right...
Page 814 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 331. Operations required to receive 0x3478AE First read from Data register Second read from Data register conditioned by RXNE=1 conditioned by RXNE=1 0xXX34 0x78AE Only the 8 LSB of the half-word are significant.
Page 815 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) PCM standard For the PCM standard, there is no need to use channel-side information. The two PCM modes (short and long frame) are available and configurable using the PCMSYNC bit in SPIx_I2SCFGR register.
Page 816 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 336. Start sequence in master mode Master I2S Philips Standard WS (O) CK (O), CKPOL = 0 CK (O), CKPOL = 1 Left sample Right sample SD (O) I2SE Master I2S MSB or LSB justified WS (O) CK (O), CKPOL = 0...
Page 817 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) 27.7.5 Clock generator The I S bit rate determines the data flow on the I S data line and the I S clock signal frequency. S bit rate = number of bits per channel × number of channels × sampling audio frequency For a 16-bit audio, left and right channel, the I S bit rate is calculated as follows: S bit rate = 16 ×...
Page 818 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Figure 338 presents the communication clock architecture. The I2SxCLK clock is provided by the reset and clock controller (RCC) of the product. The I2SxCLK clock can be asynchronous with respect to the SPI/I2S APB clock. Warning: In addition, it is mandatory to keep the I2SxCLK frequency higher or equal to the APB clock used by the SPI/I2S block.
Page 819 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Where F is the audio sampling frequency, and F is the frequency of the kernel clock I2SxCLK provided to the SPI/I2S block. Note: I2SDIV must be strictly higher than 1. The following table provides example precision values for different clock configurations. Note: Other configurations are possible that allow optimum clock precision.
Page 820 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Procedure Select the I2SDIV[7:0] bits in the SPIx_I2SPR register to define the serial clock baud rate to reach the proper audio sample frequency. The ODD bit in the SPIx_I2SPR register also has to be defined. Select the CKPOL bit to define the steady level for the communication clock.
Page 821 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length configuration, the audio value received for a right or left channel may result from one or two receptions into the Rx buffer.
Page 822 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Set the I2SMOD bit in the SPIx_I2SCFGR register to select I S mode and choose the S standard through the I2SSTD[1:0] bits, the data length through the DATLEN[1:0] bits and the number of bits per channel for the frame configuring the CHLEN bit. Select also the mode (transmission or reception) for the slave through the I2SCFG[1:0] bits in SPIx_I2SCFGR register.
Page 823 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Reception sequence The operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in Section 27.7.7: I S slave mode), where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
Page 824 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Tx buffer empty flag (TXE) When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to be transmitted.
Page 825 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) synchronization is lost, the following steps are required to recover from this state and resynchronize the external master device with the I2S slave device: Disable the I2S. Enable it again when the correct level is detected on the WS line (WS line is high in I mode or low for MSB- or LSB-justified or PCM modes.
Page 826 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 27.9 SPI and I2S registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). SPI_DR in addition can be accessed by 8-bit access. 27.9.1 SPI control register 1 (SPIx_CR1) Address offset: 0x00 Reset value: 0x0000 BIDI...
Page 827 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Bit 10 RXONLY: Receive only mode enabled. This bit enables simplex communication using a single unidirectional line to receive data exclusively. Keep BIDIMODE bit clear when receive only mode is active.This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted.
Page 828 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Bit 1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode except the case when CRC is applied at TI mode. Bit 0 CPHA: Clock phase 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge...
Page 829 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Bits 11:8 DS[3:0]: Data size These bits configure the data length for SPI transfers. 0000: Not used 0001: Not used 0010: Not used 0011: 4-bit 0100: 5-bit 0101: 6-bit 0110: 7-bit 0111: 8-bit 1000: 9-bit 1001: 10-bit...
Page 830 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Bit 2 SSOE: SS output enable 0: SS output is disabled in master mode and the SPI interface can work in multimaster configuration 1: SS output is enabled in master mode and when the SPI interface is enabled. The SPI interface cannot work in a multimaster environment.
Page 831 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Bit 7 BSY: Busy flag 0: SPI (or I2S) not busy 1: SPI (or I2S) is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware. Note: The BSY flag must be used with caution: refer to Section 27.5.10: SPI status flags Procedure for disabling the SPI on page...
Page 832 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 27.9.4 SPI data register (SPIx_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted The data register serves as an interface between the Rx and Tx FIFOs. When the data register is read, RxFIFO is accessed while the write to data register accesses TxFIFO (See Section 27.5.9: Data transmission and reception procedures).
Page 833 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RXCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPIx_CR1 register is written to 1.
Page 834 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 Bit 11 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S mode is selected Note: This bit should be configured when the SPI is disabled. Bit 10 I2SE: I2S enable 0: I2S peripheral is disabled 1: I2S peripheral is enabled Note: This bit is not used in SPI mode.
Page 835 RM0366 Serial peripheral interface / integrated interchip sound (SPI/I2S) Bit 0 CHLEN: Channel length (number of bits per audio channel) 0: 16-bit wide 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in.
Page 836 Serial peripheral interface / integrated interchip sound (SPI/I2S) RM0366 27.9.10 SPI/I2S register map Table 112 shows the SPI/I2S register map and reset values. Table 112. SPI/I2S register map and reset values Register name Offset reset value SPIx_CR1 BR [2:0] 0x00 Reset value SPIx_CR2 DS[3:0]...
Page 837 RM0366 Debug support (DBG) Debug support (DBG) 28.1 Overview ® The STM32F3xx devices are built around a Cortex -M4F core, which contains hardware extensions for advanced debugging features. The debug extensions allow the core to be stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s internal state and the system’s external state may be examined.
Page 838 Debug support (DBG) RM0366 ® The Cortex -M4F core provides integrated on-chip debug support. It is composed of: • SWJ-DP: Serial wire/JTAG debug port • AHP-AP: AHB access port • ITM: Instrumentation trace macrocell • FPB: Flash patch breakpoint • DWT: Data watchpoint trigger •...
Page 839 RM0366 Debug support (DBG) Figure 340. SWJ debug port Figure 340 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP. 28.3.1 Mechanism to select the JTAG-DP or the SW-DP By default, the JTAG-Debug Port is active.
Page 840 Debug support (DBG) RM0366 28.4.1 SWJ debug port pins Five pins are used as outputs from the STM32F3xx for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages. Table 113. SWJ debug port pins JTAG debug port SW debug port SWJ-DP pin name...
Page 841 RM0366 Debug support (DBG) To avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on the JTAG input pins: • NJTRST: Internal pull-up • JTDI: Internal pull-up • JTMS/SWDIO: Internal pull-up • TCK/SWCLK: Internal pull-down Once a JTAG IO is released by the user software, the GPIO controller takes control again. The reset states of the GPIO control registers put the I/Os in the equivalent state: •...
Page 842 Debug support (DBG) RM0366 28.4.4 Using serial wire and releasing the unused debug pins as GPIOs To use the serial wire DP to release some GPIOs, the user software must change the GPIO (PA15, PB3, and PB4) configuration mode in the GPIO_MODER PB4, which releases PA15, PB3 and PB4, which now become available as GPIOs.
Page 843 28.6.1 MCU device ID code The STM32F3xx MCUs integrate an MCU ID code. This ID identifies the ST MCU part- number and the die revision. It is part of the DBG_MCU component and is mapped on the external PPB bus (see Section 28.15 on page...
Page 844 Debug support (DBG) RM0366 Bits 31:16 REV_ID[15:0] Revision identifier This field indicates the revision of the device. For example, it is read as 0x1000 for Revision Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DEV_ID[11:0]: Device identifier This field indicates the device and its revision.
Page 845 RM0366 Debug support (DBG) Table 115. JTAG debug port data registers (continued) IR(3:0) Data register Details Debug port access register This initiates a debug port and allows access to a debug port register. – When transferring data IN: Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Page 846 Debug support (DBG) RM0366 Table 116. 32-bit debug port registers addressed through the shifted value A[3:2] (continued) Address A(3:2) value Description DP SELECT register: Used to select the current access port and the active 4-words register window. – Bits 31:24: APSEL: select the current AP –...
Page 847 RM0366 Debug support (DBG) Table 117. Packet request (8-bits) (continued) Name Description A(3:2) Address field of the DP or AP registers (refer to Table 116) Parity Single bit parity of preceding bits Stop Not driven by the host. Must be read as “1” by the target because of Park the pull-up ®...
Page 848 Access to these registers is initiated when APnDP=0 Table 120. SW-DP registers CTRLSEL bit A(3:2) of SELECT Register Notes register The manufacturer code is not set to ST code Read IDCODE 0x2BA01477 (identifies the SW-DP) Write ABORT Purpose is to: – request a system or debug power-up –...
Page 849 RM0366 Debug support (DBG) Table 120. SW-DP registers (continued) CTRLSEL bit A(3:2) of SELECT Register Notes register The purpose is to select the current access Write SELECT port and the active 4-words register window This read buffer is useful because AP accesses are posted (the result of a read AP request is available on the next AP READ...
Page 850 Debug support (DBG) RM0366 ® Table 121. Cortex -M4F AHB-AP registers Address Register name Notes offset Configures and controls transfers through the AHB AHB-AP Control and Status 0x00 interface (size, hprot, status on current transfer, address Word increment type 0x04 AHB-AP Transfer Address 0x0C AHB-AP Data Read/Write...
Page 851 RM0366 Debug support (DBG) To Halt on reset, it is necessary to: • enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control Register • enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register. 28.11 Capability of the debugger host to connect under system reset The STM32F3xx MCUs’...
Page 852 Debug support (DBG) RM0366 The DWT also provides some means to give some profiling information. For this, some counters are accessible to give the number of: • Clock cycle • Folded instructions • Load store unit (LSU) operations • Sleep cycles •...
Page 853 RM0366 Debug support (DBG) Table 123. Main ITM registers Address Register Details Write 0xC5ACCE55 to unlock Write Access to the other ITM @E0000FB0 ITM lock access registers Bits 31-24 = Always 0 Bits 23 = Busy Bits 22-16 = 7-bits ATB ID which identifies the source of the trace data.
Page 854 Debug support (DBG) RM0366 28.15 MCU debug component (DBGMCU) Arm® Arm® The MCU debug component helps the debugger provide support for: • Low-power modes • Clock control for timers, watchdog and I2C during a breakpoint • Control of the trace pins assignment 28.15.1 Debug support for low-power modes To enter low-power mode, the instruction WFI or WFE must be executed.
Page 855 RM0366 Debug support (DBG) DBGMCU_CR Address: 0xE004 2004 Only 32-bit access supported POR Reset: 0x0000 0000 (not reset by system reset) DBG_ DBG_ DBG_ Res. Res. Res. STAND STOP SLEEP Bits 31:3 Reserved, must be kept at reset value. Bit 2 DBG_STANDBY: Debug Standby mode 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
Page 856 Debug support (DBG) RM0366 28.15.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) The DBGMCU_APB1_FZ register is used to configure the MCU under DEBUG. It concerns the APB1 peripherals: • Timer clock counter freeze • I2C SMBUS timeout freeze • Window watchdog and independent watchdog counter freeze support This DBGMCU_APB1_FZ is mapped on the external PPB bus at address 0xE0042008.
Page 857 RM0366 Debug support (DBG) Bits 20:13 Reserved, must be kept at reset value. Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted 0: The independent watchdog counter clock continues even if the core is halted 1: The independent watchdog counter clock is stopped when the core is halted Bit 11 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted 0: The window watchdog counter clock continues even if the core is halted 1: The window watchdog counter clock is stopped when the core is halted...
Page 858 Debug support (DBG) RM0366 Bits 31:5 Reserved, must be kept at reset value. Bits 4:0 DBG_TIMx_STOP: TIMx counter stopped when core is halted (x=1, 8,15..17) 0: The clock of the involved timer counter is fed even if the core is halted 1: The clock of the involved timer counter is stopped when the core is halted Note: Bit1 and Bit 5 are reserved.
Page 859 RM0366 Debug support (DBG) This register is mapped on the external PPB and is reset by the PORESET (and not by the SYSTEM reset). It can be written by the debugger under SYSTEM reset. Table 125. Flexible TRACE pin assignment DBGMCU_CR register Pin assigned for:...
Page 860 Debug support (DBG) RM0366 28.15.8 TPUI frame synchronization packets The TPUI can generate two types of synchronization packets: • The Frame Synchronization packet (or Full Word Synchronization packet) It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence cannot occur at any other time provided that the ID source code 0x7F has not been used.
Page 861 RM0366 Debug support (DBG) 28.15.12 TRACECLKIN connection inside the STM32F3xx In the STM32F3xx, this TRACECLKIN input is internally connected to HCLK. This means that when in asynchronous trace mode, the application is restricted to use to time frames where the CPU frequency is stable. Note: Important: when using asynchronous trace: it is important to be aware that: The default clock of the STM32F3xx MCUs is the internal RC oscillator.
Page 862 Debug support (DBG) RM0366 28.15.13 TPIU registers The TPIU APB registers can be read and written only if the bit TRCENA of the Debug Exception and Monitor Control Register (DEMCR) is set. Otherwise, the registers are read as zero (the output of this bit enables the PCLK of the TPIU). Table 126.
Page 863 RM0366 Debug support (DBG) 28.15.14 Example of configuration • Set the bit TRCENA in the Debug Exception and Monitor Control Register (DEMCR) • Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit port size) •...
Page 864 Device electronic signature RM0366 Device electronic signature The device electronic signature is stored in the System memory area of the flash memory module, and can be read using the debug interface or by the CPU. It contains factory- programmed identification and calibration data that allow the user firmware or other external devices to automatically match to the characteristics of the STM32F3xx microcontroller.
Page 865 RM0366 Device electronic signature Bits 31:8 UID[63:40]: LOT_NUM[23:0] Lot number (ASCII encoded) Bits 7:0 UID[39:32]: WAF_NUM[7:0] Wafer number (8-bit unsigned number) Address offset: 0x08 Read only = 0xXXXX XXXX where X is factory-programmed UID[95:80] UID[79:64] Bits 31:0 UID[95:64]: LOT_NUM[55:24] Lot number (ASCII encoded) 29.2 Flash memory size data register Base address: 0x1FFF F7CC75E0...
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Page 867 RM0366 Revision history Revision history Table 128. Document revision history Date Revision Changes 23-Apr-2014 Initial release. Reset and clock control (RCC) section – Updated Section 7.4.8: APB1 peripheral clock enable register (RCC_APB1ENR), Section 7.4.5: APB1 peripheral reset register (RCC_APB1RSTR), Section 7.4.13: Clock configuration register 3 (RCC_CFGR3) and Section 7.4.14: RCC register map.
Page 868 Revision history RM0366 Table 128. Document revision history (continued) Date Revision Changes Updated I2C2 section: – Updated Figure 248: Setup and hold timings. – Updated Section 48.4.5: I2C initialization updating and adding notes in Section : I2C timings. – Updated Section 33.7.5: Timing register (I2C_TIMINGRFMPI2C_TIMINGR) SCLDEL[3:0] and SDADEL[3:0] bits description.
Page 869 RM0366 Revision history Table 128. Document revision history (continued) Date Revision Changes Updated RTC section: – Updated Section 24.3.7: RTC initialization and configuration step 3 in Section : Programming the wakeup timer. – Updated Section 24.6.4: RTC initialization and status register (RTC_ISR) bit 2 WUTWF: wakeup timer write flag.
Page 870 Revision history RM0366 Table 128. Document revision history (continued) Date Revision Changes Updated ADC section: – Updated Section 12.3.3: Clocks note, replacing option a) by option b) and removing ‘or 10’. Updated Operational amplifier section (OPAMP) section: – Updated Section Table 55.: Connections with dedicated I/O on STM32F318x8 PD14 instead of PB14 on VP1.
Page 871 RM0366 Index Index DBGMCU_IDCODE ....843 DMA_CCRx ......168 ADCx_AWD2CR .
Page 872 Index RM0366 I2C_TIMEOUTR ..... . .705 I2C_TIMINGR ......704 SPIx_CR1 .
Page 873 RM0366 Index TIM15_DIER ......537 TSC_IOASCR ......326 TIM15_DMAR .
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