ST STM32F301 6 Series Reference Manual page 231

RM0366
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG of the ADCx_CFGR register in single ADC mode:
•
DMA one shot mode (DMACFG=0).
This mode is suitable when the DMA is programmed to transfer a fixed number of data.
•
DMA circular mode (DMACFG=1)
This mode is suitable when programming the DMA in circular mode.
DMA one shot mode (DMACFG=0)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available and stops generating DMA requests once the DMA has reached the last DMA
transfer (when a transfer complete interrupt occurs - refer to DMA section) even if a
conversion has been started again.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
•
The content of the ADC data register is frozen.
•
Any ongoing conversion is aborted with partial result discarded.
•
No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
•
Scan sequence is stopped and reset.
•
The DMA is stopped.
DMA circular mode (DMACFG=1)
In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available in the data register, even if the DMA has reached the last DMA transfer. This
allows configuring the DMA in circular mode to handle a continuous analog input data
stream.
12.3.27 Dynamic low-power features
Auto-delayed conversion mode (AUTDLY)
The ADC implements an auto-delayed conversion mode controlled by the AUTDLY
configuration bit. Auto-delayed conversions are useful to simplify the software as well as to
optimize performance of an application clocked at low frequency where there would be risk
of encountering an ADC overrun.
When AUTDLY=1, a new conversion can start only if all the previous data of the same group
has been treated:
• For a regular conversion: once the ADCx_DR register has been read or if the EOC bit
has been cleared (see
•
For an injected conversion: when the JEOS bit has been cleared (see
Section : ADC overrun (OVR,
Figure
OVRMOD)).
58).
RM0366 Rev 5
Analog-to-digital converters (ADC)
Figure 59).
231/874
277