ST STM32F301 6 Series Reference Manual page 243

RM0366
Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.
12.4 ADC interrupts
For each ADC, an interrupt can be generated:
•
After ADC power-up, when the ADC is ready (flag ADRDY)
•
On the end of any conversion for regular groups (flag EOC)
•
On the end of a sequence of conversion for regular groups (flag EOS)
•
On the end of any conversion for injected groups (flag JEOC)
•
On the end of a sequence of conversion for injected groups (flag JEOS)
•
When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
•
When the end of sampling phase occurs (flag EOSMP)
•
When the data overrun occurs (flag OVR)
•
When the injected sequence context queue overflows (flag JQOVF)
Separate interrupt enable bits are available for flexibility.
ADC ready
End of conversion of a regular group
End of sequence of conversions of a regular group
End of conversion of a injected group
End of sequence of conversions of an injected group
Analog watchdog 1 status bit is set
Analog watchdog 2 status bit is set
Analog watchdog 3 status bit is set
End of sampling phase
Overrun
Injected context queue overflows
Table 41. ADC interrupts per each ADC
Interrupt event
RM0366 Rev 5
Analog-to-digital converters (ADC)
Event flag Enable control bit
ADRDY
EOC
EOS
JEOC
JEOS
AWD1
AWD2
AWD3
EOSMP
OVR
JQOVF
ADRDYIE
EOCIE
EOSIE
JEOCIE
JEOSIE
AWD1IE
AWD2IE
AWD3IE
EOSMPIE
OVRIE
JQOVFIE
243/874
277