ST STM32F301 6 Series Reference Manual page 668

Inter-integrated circuit interface (I2C)
25.4.9 I2C controller mode
I2C controller initialization
Before enabling the peripheral, the I2C controller clock must be configured, by setting the
SCLH and SCLL bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
A clock synchronization mechanism is implemented in order to support multicontroller
environment and target clock stretching.
In order to allow clock synchronization:
•
The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
•
The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
I2C detects its own SCL low level after a
SCL input noise filters (analog and digital), and SCL synchronization to the I2CxCLK clock.
I2C releases SCL to high level once the SCLL counter reaches the value programmed in the
SCLL[7:0] bitfield of the I2C_TIMINGR register.
I2C detects its own SCL high level after a
SCL input noise filters (analog and digital), and SCL synchronization to the I2CxCLK clock.
I2C ties SCL to low level once the SCLH counter reaches the value programmed in the
SCLH[7:0] bitfield of the I2C_TIMINGR register.
Consequently the controller clock period is:
t t
SCL = SYNC1
The duration of t
•
SCL falling slope
•
input delay induced by the analog filter (when enabled)
•
input delay induced by the digital filter (when enabled): DNF[3:0]
•
delay due to SCL synchronization with the I2CCLK clock (two to three I2CCLK periods)
The duration of t
•
SCL rising slope
•
input delay induced by the analog filter (when enabled)
•
input delay induced by the digital filter (when enabled): DNF[3:0]
•
delay due to SCL synchronization with the I2CCLK clock (two to three I2CCLK periods)
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+ t {[(SCLH+ 1) + (SCLL+ 1)] x (PRESC+ 1) x t
SYNC2 +
depends upon:
SYNC1
depends upon:
SYNC2
RM0366 Rev 5
delay depending on the SCL falling edge,
t
SYNC1
delay depending on the SCL rising edge,
t
SYNC2
RM0366
}
I2CCLK
x t
I2CCLK
x t
I2CCLK