ST STM32F301 6 Series Reference Manual page 850

Debug support (DBG)
Address
offset
0x00
0x04
0x0C
0x10
0x14
0x18
0x1C
0xF8
0xFC
Refer to the Cortex
28.10 Core debug
Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can
access these registers directly over the internal Private Peripheral Bus (PPB).
It consists of 4 registers:
Register
DHCSR
DCRSR
DCRDR
DEMCR
Note: Important: these registers are not reset by a system reset. They are only reset by a power-
on reset.
Refer to the Cortex
850/874
Table 121. Cortex
Register name
AHB-AP Control and Status
Word
AHB-AP Transfer Address
AHB-AP Data Read/Write
AHB-AP Banked Data 0
AHB-AP Banked Data 1
AHB-AP Banked Data 2
AHB-AP Banked Data 3
AHB-AP Debug ROM Address Base Address of the debug interface
AHB-AP ID Register
®
-M4F r0p1 TRM for further details.
Table 122. Core debug registers
The 32-bit Debug Halting Control and Status Register
This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
This provides Vector Catching and Debug Monitor Control. This register contains a
bit named TRCENA which enable the use of a TRACE.
®
-M4F r0p1 TRM for further details.
RM0366 Rev 5
®
-M4F AHB-AP registers
Configures and controls transfers through the AHB
interface (size, hprot, status on current transfer, address
increment type
Directly maps the 4 aligned data words without rewriting
the Transfer Address Register.
Description
RM0366
Notes
-
-
-