ST STM32F301 6 Series Reference Manual page 38

System and memory overview
2 System and memory overview
2.1 System architecture
The STM32F318x8 main system consists of:
•
Four masters:
–
–
–
–
•
Six slaves:
–
–
–
–
–
–
The interconnection uses a multilayer AHB bus architecture as shown in figures 1.
Arm
Cortex-M4
GPDMA1
FLASH 64 K
64 bits
38/874
®
Cortex -M4 core I-bus
®
Cortex -M4 core D-bus
®
Cortex -M4 core S-bus
DMA1 (general-purpose DMA)
Internal flash memory on the DCode
Internal flash memory on ICode
Up to 16-Kbyte internal SRAM
AHB to APBx (APB1 or APB2), which connect all the APB peripherals
AHB dedicated to GPIO ports
ADC1
Figure 1. System architecture
I-bus
D-bus
S-bus
DMA
M0
ICODE
FLITF
DCODE
SRAM
up to 16 KB
BusMatrix-S
M1 M2 M3
M4
RM0366 Rev 5
M5
AHB dedicated
to GPIO ports
ADC1
RCC, TSC, CRC and
AHB to APB 1 and APB2
RM0366
MS33186V3