ST STM32F301 6 Series Reference Manual page 694

Inter-integrated circuit interface (I2C)
If the received address matches the device own address, I2C stretches SCL low until the
device wakes up. The stretch is released when the ADDR flag is cleared by software. Then
the transfer goes on normally.
If the address does not match, the HSI oscillator is stopped again and the device does not
wake up.
Note: When the system clock is used as I2C clock, or when WUPEN = 0, the HSI oscillator does
not start upon receiving START condition.
Only an ADDR interrupt can wake the device up. Therefore, do not enter Stop mode when
I2C is performing a transfer, either as a controller or as an addressed target after the ADDR
flag is set. This can be managed by clearing the SLEEPDEEP bit in the ADDR interrupt
routine and setting it again only after the STOPF flag is set.
Caution: The digital filter is not compatible with the wake-up from Stop mode feature. Before entering
Stop mode with the WUPEN bit set, deactivate the digital filter, by writing zero to the
DNF[3:0] bitfield.
Caution: The feature is only available when the HSI oscillator is selected as the I2C clock.
Caution: Clock stretching must be enabled (NOSTRETCH = 0) to ensure proper operation of the
wake-up from Stop mode feature.
Caution: If the wake-up from Stop mode is disabled (WUPEN = 0), the I2C peripheral must be
disabled before entering Stop mode (PE = 0).
25.4.17 Error conditions
The following errors are the conditions that can cause the communication to fail.
Bus error (BERR)
A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of nine SCL clock pulses. START or STOP condition is detected when an
SDA edge occurs while SCL is high.
The bus error flag is set only if the I2C peripheral is involved in the transfer as controller or
addressed target (that is, not during the address phase in target mode).
In case of a misplaced START or RESTART detection in target mode, the I2C peripheral
enters address recognition state like for a correct START condition.
When a bus error is detected, the BERR flag of the I2C_ISR register is set, and an interrupt
is generated if the ERRIE bit of the I2C_CR1 register is set.
Arbitration loss (ARLO)
An arbitration loss is detected when a high level is sent on the SDA line, but a low level is
sampled on the SCL rising edge.
In controller mode, arbitration loss is detected during the address phase, data phase and
data acknowledge phase. In this case, the SDA and SCL lines are released, the START
control bit is cleared by hardware and the controller switches automatically to target mode.
In target mode, arbitration loss is detected during data phase and data acknowledge phase.
In this case, the transfer is stopped and the SCL and SDA lines are released.
When an arbitration loss is detected, the ARLO flag of the I2C_ISR register is set and an
interrupt is generated if the ERRIE bit of the I2C_CR1 register is set.
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