ST STM32F301 6 Series Reference Manual page 175

RM0366
11 Interrupts and events
11.1 Nested vectored interrupt controller (NVIC)
11.1.1 NVIC main features
•
66 maskable interrupt channels (not including the sixteen Cortex-M4 with FPU interrupt
lines)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
Low-latency exception and interrupt handling
•
Power management control
•
Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the PM0214 programming manual for
Cortex-M4 products.
11.1.2 SysTick calibration value register
The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with
the SysTick clock set to 9 MHz (max f
11.1.3 Interrupt and exception vectors
Type of
priority
- - -
- -3 Fixed
- -2 Fixed
- -1 Fixed
- 0 Settable
- 1 Settable
- 2 Settable
- - -
- 3 Settable
- 5 Settable
Table 28. STM32F3xx vector table
Acronym
-
Reset
NMI
HardFault
MemManage
BusFault
UsageFault
-
SVCall
PendSV
/8).
HCLK
Description
Reserved
Reset
Non maskable interrupt. The RCC Clock
Security System (CSS) is linked to the NMI
vector.
All class of fault
Memory management
Pre-fetch fault, memory access fault
Undefined instruction or illegal state
Reserved
System service call via SWI instruction
Pendable request for system service
RM0366 Rev 5
Interrupts and events
Address
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 0010
0x0000 0014
0x0000 0018
0x0000 001C -
0x0000 0028
0x0000 002C
0x0000 0038
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