ST STM32F301 6 Series Reference Manual page 455

RM0366
OC2'
OC1'
OC2
OC1
OC1REF
OC2REF
OC1REF'
OC2REF'
OC1REFC
OC1REFC'
18.3.12 Clearing the OCxREF signal on an external event
The OCxREF signal of a given channel can be cleared when a high level is applied on the
ocref_clr_int input (OCxCE enable bit in the corresponding TIMx_CCMRx register set to 1).
OCxREF remains low until the next transition to the active state, on the following PWM
cycle. This function can only be used in Output compare and PWM modes. It does not work
in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR
after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
The OCxREF signal for a given channel can be reset by applying a high level on the ETRF
input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF
remains low until the next transition to the active state, on the following PWM cycle.
This function can be used only in the output compare and PWM modes. It does not work in
forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be
used for current handling. In this case, ETR must be configured as follows:
Figure 182. Combined PWM mode on channels 1 and 3
OC1REFC = OC1REF AND OC2REF
OC1REFC' = OC1REF' OR OC2REF'
RM0366 Rev 5
General-purpose timer (TIM2)
MS31094V1
455/874
495