ST STM32F301 6 Series Reference Manual page 408

Advanced-control timer (TIM1)
Bits 24, 14:12 OC4M[3:0]: Output compare 4 mode
Refer to OC3M[3:0] description.
Bit 11 OC4PE: Output compare 4 preload enable
Refer to OC1PE description.
Bit 10 OC4FE: Output compare 4 fast enable
Refer to OC1FE description.
Bits 9:8 CC4S[1:0]: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = '0' in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Refer to OC1CE description.
Bits 16, 6:4 OC3M[3:0]: Output compare 3 mode
Refer to OC1M[3:0] description.
Bit 3 OC3PE: Output compare 3 preload enable
Refer to OC1PE description.
Bit 2 OC3FE: Output compare 3 fast enable
Refer to OC1FE description.
Bits 1:0 CC3S[1:0]: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = '0' in TIMx_CCER).
17.4.11 TIM1 capture/compare enable register
(TIM1_CCER)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
CC4NP Res. CC4P CC4E
rw rw
Bits 31:22 Reserved, must be kept at reset value.
408/874
28 27 26 25
Res. Res. Res.
12 11 10 9
CC3NP CC3NE CC3P
rw rw rw rw
24 23 22
Res. Res. Res. CC6P
8 7 6
CC3E CC2NP CC2NE CC2P
rw rw rw
RM0366 Rev 5
21 20 19 18
CC6E Res. Res.
rw rw
5 4 3 2
CC2E CC1NP CC1NE
rw rw rw rw
RM0366
17 16
CC5P CC5E
rw rw
1 0
CC1P CC1E
rw rw