ST STM32F301 6 Series Reference Manual page 564

General-purpose timers (TIM15/TIM16/TIM17)
19.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)
Address offset: 0x20
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CC1NP: Capture/Compare 1 complementary output polarity
CC1 channel configured as output:
CC1 channel configured as input:
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits
564/874
12 11 10 9
Res. Res. Res.
0: OC1N active high
1: OC1N active low
This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer
to the description of CC1P.
in TIMx_BDTR register) and CC1S="00" (the channel is configured in output).
On channels that have a complementary output, this bit is preloaded. If the CCPC bit is
set in the TIMx_CR2 register then the CC1NP active bit takes the new value from the
preloaded bit only when a commutation event is generated.
8 7 6
Res. Res. Res.
RM0366 Rev 5
5 4 3 2
Res. Res. CC1NP CC1NE
rw rw
RM0366
1 0
CC1P CC1E
rw rw