ST STM32F301 6 Series Reference Manual page 138

General-purpose I/Os (GPIO)
8.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to D and F)
Address offset: 0x10
Reset value: 0x0000 XXXX
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
IDR15 IDR14 IDR13 IDR12
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDR[15:0]: Port x input data I/O pin y (y = 15 to 0)
8.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to D and F)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODR[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to
138/874
27 26 25
Res. Res. Res.
11 10 9
IDR11 IDR10 IDR9
r r r r
These bits are read-only. They contain the input value of the corresponding I/O port.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
ODR9
rw rw rw rw
the GPIOx_BSRR register (x = A..F).
24 23 22
Res. Res. Res. Res.
8 7 6
IDR8 IDR7 IDR6 IDR5
r r r
24 23 22
Res. Res. Res.
8 7 6
ODR8 ODR7 ODR6 ODR5
rw rw rw
RM0366 Rev 5
21 20 19 18
Res. Res. Res.
5 4 3 2
IDR4 IDR3 IDR2
r r r r
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ODR4 ODR3 ODR2
rw rw rw rw
RM0366
17 16
Res. Res.
1 0
IDR1 IDR0
r r
17 16
Res. Res.
1 0
ODR1 ODR0
rw rw