ST STM32F301 6 Series Reference Manual page 50

Embedded flash memory
Main flash memory programming
The main flash memory can be programmed 16 bits at a time. The program operation is
started when the CPU writes a half-word into a main flash memory address with the PG bit
of the FLASH_CR register set. Any attempt to write data that are not half-word long results
in a bus error generating a Hard Fault interrupt.
The flash memory interface preliminarily reads the value at the addressed main flash
memory location and checks that it has been erased. If not, the program operation is
skipped and a warning is issued by the PGERR bit in FLASH_SR register (the only
exception to this is when 0x0000 is programmed. In this case, the location is correctly
programmed to 0x0000 and the PGERR bit is not set). If the addressed main flash memory
location is write-protected by the FLASH_WRPR register, the program operation is skipped
and a warning is issued by the WRPRTERR bit in the FLASH_SR register. The end of the
program operation is indicated by the EOP bit in the FLASH_SR register.
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Figure 2. Programming procedure
Read FLASH_CR_LOCK
FLASH_CR_LOCK
= 1
No
Write FLASH_CR_PG to 1
Perform half-word write at the
desired address
FLASH_SR_BSY
= 1
No
Check the programmed value
by reading the programmed
address
RM0366 Rev 5
Yes
Perform unlock sequency
Yes
RM0366
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