ST STM32F301 6 Series Reference Manual page 333

RM0366
CK_TIM18 from RCC
TIMx_ETR
XOR
TI1
TIMx_CH1
TI2
TIMx_CH2
TI3
TIMx_CH3
TI4
TIMx_CH4
BRK
TIMx_BKIN
BRK_ACTH
Internal break event sources (see note below)
BRK2
Polarity selection
TIMx_BKIN2
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
Figure 92. Advanced-control timer block diagram
Internal clock (CK_INT)
ETRP
Polarity selection & edge
ETR
detector & prescaler
ITR0
ITR1
ITR2
ITR3
TI1F_ED
CK_PSC
TI1FP1
IC1
Input filter &
TI1FP2
Prescaler
edge detector
TRC
TI2FP1
IC2
Input filter &
TI2FP2
Prescaler
edge detector
TRC
TI3FP3
IC3
Input filter &
TI3FP4
Prescaler
edge detector
TRC
TI4FP3
Input filter & IC4
TI4FP4
Prescaler
edge detector
TRC
Polarity selection
filter
filter
ETRF
Input
filter
TRG
ITR
TRC TRGI
TI1FP1
TI2FP2
U
Auto-reload register
Stop, clear or up/down
PSC CK_CNT
+/-
CNT counter
prescaler
CC1I
U
IC1PS
Capture/Compare 1 register
CC2I
U
IC2PS
Capture/Compare 2 register
CC3I
U
IC3PS
Capture/Compare 3 register
CC4I
U
IC4PS
Capture/Compare 4 register
Capture/Compare 5 register
Capture/Compare 6 register
ETRF
BI
RM0366 Rev 5
Advanced-control timer (TIM1)
Trigger
TRGO
controller
to other timersto DAC/ADC
Slave
Reset, enable, up/down, count
controller
mode
Encoder
Interface
REP register
Repetition
counter
DTG registers
CC1I
OC1REF
Output
DTG
control
CC2I
Output
OC2REF
control
DTG
CC3I
OC3REF
Output
DTG
control
CC4I
Output
OC4REF
control
Output
OC5REF
control
Output
OC6REF
control
UI
U
TIMx_CH1
OC1
TIMx_CH1N
OC1N
TIMx_CH2
OC2
TIMx_CH2N
OC2N
TIMx_CH3
OC3
TIMx_CH3N
OC3N
OC4
TIMx_CH4
OC5
OC6
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