ST STM32F301 6 Series Reference Manual page 638

Real-time clock (RTC)
24.6.14 RTC time-stamp sub second register (RTC_TSSSR)
The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event
occurred.
638/874
28 27 26 25
Res. Res. Res.
12 11 10 9
r r r r
24 23 22
Res. Res. Res.
8 7 6
SS[15:0]
r r r
RM0366 Rev 5
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
r r r r
RM0366
17 16
Res. Res.
1 0
r r