ST STM32F301 6 Series Reference Manual page 233

RM0366
Figure 58. AUTODLY=1, regular conversion in continuous mode, software trigger
ADSTART (1)
EOC
EOS
ADSTP
ADC_DR read access
ADC state RDY
ADC_DR
by SW
1. AUTDLY=1
2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, CHANNELS = 1,2,3
3. Injected configuration DISABLED
Figure 59. AUTODLY=1, regular HW conversions interrupted by injected conversions
Regular
trigger
ADC state
RDY CH1
regular
EOC
EOS
ADC_DR
read access
ADC_DR
Injected
trigger
JEOS
ADC_JDR1
ADC_JDR2
by s/w
1. AUTDLY=1
2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6
CH1
DLY CH2 DLY
D1
by HW
(DISCEN=0; JDISCEN=0)
Ignored
DLY CH2
DLY (CH1)
DLY (CH2)
D1
by h/w
DLY
CH3
D2 D3
Not ignored
(occurs during injected sequence)
DLY CH5 CH6
regular injected regular
D2
Ignored
Indicative timings
RM0366 Rev 5
Analog-to-digital converters (ADC)
CH1 DLY
STOP
D1
Indicative timings
CH3 DLY CH1
regular
injected
DLY (CH3)
D3
DLY (inj)
D5
D6
RDY
MS31020V1
DLY CH2
regular
DLY (CH1)
D1
MS31021V2
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